1*67e74705SXin Li // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-feature +neon \
2*67e74705SXin Li // RUN: -S -emit-llvm -o - %s \
3*67e74705SXin Li // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
4*67e74705SXin Li
5*67e74705SXin Li // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
6*67e74705SXin Li // RUN: -target-feature +v8.1a -S -emit-llvm -o - %s \
7*67e74705SXin Li // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
8*67e74705SXin Li
9*67e74705SXin Li // REQUIRES: arm-registered-target,aarch64-registered-target
10*67e74705SXin Li
11*67e74705SXin Li #include <arm_neon.h>
12*67e74705SXin Li
13*67e74705SXin Li // CHECK-LABEL: test_vqrdmlah_s16
test_vqrdmlah_s16(int16x4_t a,int16x4_t b,int16x4_t c)14*67e74705SXin Li int16x4_t test_vqrdmlah_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
15*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
16*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
17*67e74705SXin Li
18*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
19*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
20*67e74705SXin Li return vqrdmlah_s16(a, b, c);
21*67e74705SXin Li }
22*67e74705SXin Li
23*67e74705SXin Li // CHECK-LABEL: test_vqrdmlah_s32
test_vqrdmlah_s32(int32x2_t a,int32x2_t b,int32x2_t c)24*67e74705SXin Li int32x2_t test_vqrdmlah_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
25*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
26*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
27*67e74705SXin Li
28*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
29*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
30*67e74705SXin Li return vqrdmlah_s32(a, b, c);
31*67e74705SXin Li }
32*67e74705SXin Li
33*67e74705SXin Li // CHECK-LABEL: test_vqrdmlahq_s16
test_vqrdmlahq_s16(int16x8_t a,int16x8_t b,int16x8_t c)34*67e74705SXin Li int16x8_t test_vqrdmlahq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {
35*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
36*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
37*67e74705SXin Li
38*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
39*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
40*67e74705SXin Li return vqrdmlahq_s16(a, b, c);
41*67e74705SXin Li }
42*67e74705SXin Li
43*67e74705SXin Li // CHECK-LABEL: test_vqrdmlahq_s32
test_vqrdmlahq_s32(int32x4_t a,int32x4_t b,int32x4_t c)44*67e74705SXin Li int32x4_t test_vqrdmlahq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {
45*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
46*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
47*67e74705SXin Li
48*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
49*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
50*67e74705SXin Li return vqrdmlahq_s32(a, b, c);
51*67e74705SXin Li }
52*67e74705SXin Li
53*67e74705SXin Li // CHECK-LABEL: test_vqrdmlah_lane_s16
test_vqrdmlah_lane_s16(int16x4_t a,int16x4_t b,int16x4_t c)54*67e74705SXin Li int16x4_t test_vqrdmlah_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
55*67e74705SXin Li // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
56*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
57*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqadds.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
58*67e74705SXin Li
59*67e74705SXin Li // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
60*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
61*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
62*67e74705SXin Li return vqrdmlah_lane_s16(a, b, c, 3);
63*67e74705SXin Li }
64*67e74705SXin Li
65*67e74705SXin Li // CHECK-LABEL: test_vqrdmlah_lane_s32
test_vqrdmlah_lane_s32(int32x2_t a,int32x2_t b,int32x2_t c)66*67e74705SXin Li int32x2_t test_vqrdmlah_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
67*67e74705SXin Li // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>
68*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
69*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqadds.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
70*67e74705SXin Li
71*67e74705SXin Li // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>
72*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
73*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
74*67e74705SXin Li return vqrdmlah_lane_s32(a, b, c, 1);
75*67e74705SXin Li }
76*67e74705SXin Li
77*67e74705SXin Li // CHECK-LABEL: test_vqrdmlahq_lane_s16
test_vqrdmlahq_lane_s16(int16x8_t a,int16x8_t b,int16x4_t c)78*67e74705SXin Li int16x8_t test_vqrdmlahq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {
79*67e74705SXin Li // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
80*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
81*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqadds.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
82*67e74705SXin Li
83*67e74705SXin Li // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
84*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
85*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
86*67e74705SXin Li return vqrdmlahq_lane_s16(a, b, c, 3);
87*67e74705SXin Li }
88*67e74705SXin Li
89*67e74705SXin Li // CHECK-LABEL: test_vqrdmlahq_lane_s32
test_vqrdmlahq_lane_s32(int32x4_t a,int32x4_t b,int32x2_t c)90*67e74705SXin Li int32x4_t test_vqrdmlahq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {
91*67e74705SXin Li // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
92*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
93*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
94*67e74705SXin Li
95*67e74705SXin Li // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
96*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
97*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
98*67e74705SXin Li return vqrdmlahq_lane_s32(a, b, c, 1);
99*67e74705SXin Li }
100*67e74705SXin Li
101*67e74705SXin Li // CHECK-LABEL: test_vqrdmlsh_s16
test_vqrdmlsh_s16(int16x4_t a,int16x4_t b,int16x4_t c)102*67e74705SXin Li int16x4_t test_vqrdmlsh_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
103*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
104*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
105*67e74705SXin Li
106*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
107*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
108*67e74705SXin Li return vqrdmlsh_s16(a, b, c);
109*67e74705SXin Li }
110*67e74705SXin Li
111*67e74705SXin Li // CHECK-LABEL: test_vqrdmlsh_s32
test_vqrdmlsh_s32(int32x2_t a,int32x2_t b,int32x2_t c)112*67e74705SXin Li int32x2_t test_vqrdmlsh_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
113*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
114*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
115*67e74705SXin Li
116*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
117*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
118*67e74705SXin Li return vqrdmlsh_s32(a, b, c);
119*67e74705SXin Li }
120*67e74705SXin Li
121*67e74705SXin Li // CHECK-LABEL: test_vqrdmlshq_s16
test_vqrdmlshq_s16(int16x8_t a,int16x8_t b,int16x8_t c)122*67e74705SXin Li int16x8_t test_vqrdmlshq_s16(int16x8_t a, int16x8_t b, int16x8_t c) {
123*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
124*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
125*67e74705SXin Li
126*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
127*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
128*67e74705SXin Li return vqrdmlshq_s16(a, b, c);
129*67e74705SXin Li }
130*67e74705SXin Li
131*67e74705SXin Li // CHECK-LABEL: test_vqrdmlshq_s32
test_vqrdmlshq_s32(int32x4_t a,int32x4_t b,int32x4_t c)132*67e74705SXin Li int32x4_t test_vqrdmlshq_s32(int32x4_t a, int32x4_t b, int32x4_t c) {
133*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
134*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
135*67e74705SXin Li
136*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
137*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
138*67e74705SXin Li return vqrdmlshq_s32(a, b, c);
139*67e74705SXin Li }
140*67e74705SXin Li
141*67e74705SXin Li // CHECK-LABEL: test_vqrdmlsh_lane_s16
test_vqrdmlsh_lane_s16(int16x4_t a,int16x4_t b,int16x4_t c)142*67e74705SXin Li int16x4_t test_vqrdmlsh_lane_s16(int16x4_t a, int16x4_t b, int16x4_t c) {
143*67e74705SXin Li // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
144*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
145*67e74705SXin Li // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqsubs.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
146*67e74705SXin Li
147*67e74705SXin Li // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
148*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
149*67e74705SXin Li // CHECK-AARCH64: call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}})
150*67e74705SXin Li return vqrdmlsh_lane_s16(a, b, c, 3);
151*67e74705SXin Li }
152*67e74705SXin Li
153*67e74705SXin Li // CHECK-LABEL: test_vqrdmlsh_lane_s32
test_vqrdmlsh_lane_s32(int32x2_t a,int32x2_t b,int32x2_t c)154*67e74705SXin Li int32x2_t test_vqrdmlsh_lane_s32(int32x2_t a, int32x2_t b, int32x2_t c) {
155*67e74705SXin Li // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>
156*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
157*67e74705SXin Li // CHECK-ARM: call <2 x i32> @llvm.arm.neon.vqsubs.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
158*67e74705SXin Li
159*67e74705SXin Li // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <2 x i32> <i32 1, i32 1>
160*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
161*67e74705SXin Li // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> {{%.*}}, <2 x i32> {{%.*}})
162*67e74705SXin Li return vqrdmlsh_lane_s32(a, b, c, 1);
163*67e74705SXin Li }
164*67e74705SXin Li
165*67e74705SXin Li // CHECK-LABEL: test_vqrdmlshq_lane_s16
test_vqrdmlshq_lane_s16(int16x8_t a,int16x8_t b,int16x4_t c)166*67e74705SXin Li int16x8_t test_vqrdmlshq_lane_s16(int16x8_t a, int16x8_t b, int16x4_t c) {
167*67e74705SXin Li // CHECK-ARM: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
168*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
169*67e74705SXin Li // CHECK-ARM: call <8 x i16> @llvm.arm.neon.vqsubs.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
170*67e74705SXin Li
171*67e74705SXin Li // CHECK-AARCH64: shufflevector <4 x i16> {{%.*}}, <4 x i16> {{%.*}}, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
172*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
173*67e74705SXin Li // CHECK-AARCH64: call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> {{%.*}}, <8 x i16> {{%.*}})
174*67e74705SXin Li return vqrdmlshq_lane_s16(a, b, c, 3);
175*67e74705SXin Li }
176*67e74705SXin Li
177*67e74705SXin Li // CHECK-LABEL: test_vqrdmlshq_lane_s32
test_vqrdmlshq_lane_s32(int32x4_t a,int32x4_t b,int32x2_t c)178*67e74705SXin Li int32x4_t test_vqrdmlshq_lane_s32(int32x4_t a, int32x4_t b, int32x2_t c) {
179*67e74705SXin Li // CHECK-ARM: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
180*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
181*67e74705SXin Li // CHECK-ARM: call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
182*67e74705SXin Li
183*67e74705SXin Li // CHECK-AARCH64: shufflevector <2 x i32> {{%.*}}, <2 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
184*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
185*67e74705SXin Li // CHECK-AARCH64: call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> {{%.*}}, <4 x i32> {{%.*}})
186*67e74705SXin Li return vqrdmlshq_lane_s32(a, b, c, 1);
187*67e74705SXin Li }
188