1*67e74705SXin Li // REQUIRES: arm-registered-target
2*67e74705SXin Li // RUN: %clang_cc1 -triple armv7 -target-feature +neon %s -emit-llvm -o /dev/null
3*67e74705SXin Li
4*67e74705SXin Li char bar();
5*67e74705SXin Li
t1(int x,char y)6*67e74705SXin Li void t1(int x, char y) {
7*67e74705SXin Li __asm__ volatile("mcr p15, 0, %1, c9, c12, 5;"
8*67e74705SXin Li "mrc p15, 0, %0, c9, c13, 2;"
9*67e74705SXin Li : "=r" (x)
10*67e74705SXin Li : "r" (bar())); // no warning
11*67e74705SXin Li __asm__ volatile("foo %0, %1"
12*67e74705SXin Li : "+r" (x),
13*67e74705SXin Li "+r" (y)
14*67e74705SXin Li :);
15*67e74705SXin Li __asm__ volatile("ldrb %0, [%1]" : "=r" (y) : "r" (x)); // no warning
16*67e74705SXin Li }
17*67e74705SXin Li
18*67e74705SXin Li // <rdar://problem/12284092>
19*67e74705SXin Li typedef __attribute__((neon_vector_type(2))) long long int64x2_t;
20*67e74705SXin Li typedef struct int64x2x4_t {
21*67e74705SXin Li int64x2_t val[4];
22*67e74705SXin Li } int64x2x4_t;
t2(const long long a[])23*67e74705SXin Li int64x2x4_t t2(const long long a[]) {
24*67e74705SXin Li int64x2x4_t r;
25*67e74705SXin Li __asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }"
26*67e74705SXin Li : [r0] "=r"(r.val[0]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
27*67e74705SXin Li [r1] "=r"(r.val[1]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
28*67e74705SXin Li [r2] "=r"(r.val[2]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
29*67e74705SXin Li [r3] "=r"(r.val[3]) // expected-warning {{value size does not match register size specified by the constraint and modifier}}
30*67e74705SXin Li : [a] "r"(a));
31*67e74705SXin Li return r;
32*67e74705SXin Li }
33