1*67e74705SXin Li // REQUIRES: arm-registered-target
2*67e74705SXin Li // RUN: not %clang_cc1 -triple armv7 -target-feature +neon %s -S -o /dev/null 2>&1 | FileCheck %s
3*67e74705SXin Li
4*67e74705SXin Li // rdar://13446483
5*67e74705SXin Li typedef __attribute__((neon_vector_type(2))) long long int64x2_t;
6*67e74705SXin Li typedef struct int64x2x4_t {
7*67e74705SXin Li int64x2_t val[4];
8*67e74705SXin Li } int64x2x4_t;
t1(const long long a[])9*67e74705SXin Li int64x2x4_t t1(const long long a[]) {
10*67e74705SXin Li int64x2x4_t r;
11*67e74705SXin Li __asm__("vldm %[a], { %q[r0], %q[r1], %q[r2], %q[r3] }"
12*67e74705SXin Li : [r0] "=r"(r.val[0]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
13*67e74705SXin Li [r1] "=r"(r.val[1]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
14*67e74705SXin Li [r2] "=r"(r.val[2]), // expected-warning {{value size does not match register size specified by the constraint and modifier}}
15*67e74705SXin Li [r3] "=r"(r.val[3]) // expected-warning {{value size does not match register size specified by the constraint and modifier}}
16*67e74705SXin Li : [a] "r"(a));
17*67e74705SXin Li return r;
18*67e74705SXin Li }
19*67e74705SXin Li // We should see all four errors, rather than report a fatal error after the first.
20*67e74705SXin Li // CHECK: error: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type
21*67e74705SXin Li // CHECK: error: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type
22*67e74705SXin Li // CHECK: error: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type
23*67e74705SXin Li // CHECK: error: non-trivial scalar-to-vector conversion, possible invalid constraint for vector type
24