xref: /aosp_15_r20/external/clang/test/CodeGen/aarch64-inline-asm.c (revision 67e74705e28f6214e480b399dd47ea732279e315)
1*67e74705SXin Li // RUN: %clang_cc1 -triple arm64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
2*67e74705SXin Li 
3*67e74705SXin Li // The only part clang really deals with is the lvalue/rvalue
4*67e74705SXin Li // distinction on constraints. It's sufficient to emit llvm and make
5*67e74705SXin Li // sure that's sane.
6*67e74705SXin Li 
7*67e74705SXin Li long var;
8*67e74705SXin Li 
test_generic_constraints(int var32,long var64)9*67e74705SXin Li void test_generic_constraints(int var32, long var64) {
10*67e74705SXin Li     asm("add %0, %1, %1" : "=r"(var32) : "0"(var32));
11*67e74705SXin Li // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i32, i32*
12*67e74705SXin Li // CHECK: call i32 asm "add $0, $1, $1", "=r,0"(i32 [[R32_ARG]])
13*67e74705SXin Li 
14*67e74705SXin Li     asm("add %0, %1, %1" : "=r"(var64) : "0"(var64));
15*67e74705SXin Li // CHECK: [[R32_ARG:%[a-zA-Z0-9]+]] = load i64, i64*
16*67e74705SXin Li // CHECK: call i64 asm "add $0, $1, $1", "=r,0"(i64 [[R32_ARG]])
17*67e74705SXin Li 
18*67e74705SXin Li     asm("ldr %0, %1" : "=r"(var32) : "m"(var));
19*67e74705SXin Li     asm("ldr %0, [%1]" : "=r"(var64) : "r"(&var));
20*67e74705SXin Li // CHECK: call i32 asm "ldr $0, $1", "=r,*m"(i64* @var)
21*67e74705SXin Li // CHECK: call i64 asm "ldr $0, [$1]", "=r,r"(i64* @var)
22*67e74705SXin Li }
23*67e74705SXin Li 
24*67e74705SXin Li float f;
25*67e74705SXin Li double d;
test_constraint_w()26*67e74705SXin Li void test_constraint_w() {
27*67e74705SXin Li     asm("fadd %s0, %s1, %s1" : "=w"(f) : "w"(f));
28*67e74705SXin Li // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f
29*67e74705SXin Li // CHECK: call float asm "fadd ${0:s}, ${1:s}, ${1:s}", "=w,w"(float [[FLT_ARG]])
30*67e74705SXin Li 
31*67e74705SXin Li     asm("fadd %d0, %d1, %d1" : "=w"(d) : "w"(d));
32*67e74705SXin Li // CHECK: [[DBL_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d
33*67e74705SXin Li // CHECK: call double asm "fadd ${0:d}, ${1:d}, ${1:d}", "=w,w"(double [[DBL_ARG]])
34*67e74705SXin Li }
35*67e74705SXin Li 
test_constraints_immed(void)36*67e74705SXin Li void test_constraints_immed(void) {
37*67e74705SXin Li     asm("add x0, x0, %0" : : "I"(4095) : "x0");
38*67e74705SXin Li     asm("and w0, w0, %0" : : "K"(0xaaaaaaaa) : "w0");
39*67e74705SXin Li     asm("and x0, x0, %0" : : "L"(0xaaaaaaaaaaaaaaaa) : "x0");
40*67e74705SXin Li // CHECK: call void asm sideeffect "add x0, x0, $0", "I,~{x0}"(i32 4095)
41*67e74705SXin Li // CHECK: call void asm sideeffect "and w0, w0, $0", "K,~{w0}"(i32 -1431655766)
42*67e74705SXin Li // CHECK: call void asm sideeffect "and x0, x0, $0", "L,~{x0}"(i64 -6148914691236517206)
43*67e74705SXin Li }
44*67e74705SXin Li 
test_constraint_S(void)45*67e74705SXin Li void test_constraint_S(void) {
46*67e74705SXin Li     int *addr;
47*67e74705SXin Li     asm("adrp %0, %A1\n\t"
48*67e74705SXin Li         "add %0, %0, %L1" : "=r"(addr) : "S"(&var));
49*67e74705SXin Li // CHECK: call i32* asm "adrp $0, ${1:A}\0A\09add $0, $0, ${1:L}", "=r,S"(i64* @var)
50*67e74705SXin Li }
51*67e74705SXin Li 
test_constraint_Q(void)52*67e74705SXin Li void test_constraint_Q(void) {
53*67e74705SXin Li     int val;
54*67e74705SXin Li     asm("ldxr %0, %1" : "=r"(val) : "Q"(var));
55*67e74705SXin Li // CHECK: call i32 asm "ldxr $0, $1", "=r,*Q"(i64* @var)
56*67e74705SXin Li }
57