1*9a0e4156SSadaf Ebrahimi(* Capstone Disassembly Engine 2*9a0e4156SSadaf Ebrahimi * By Nguyen Anh Quynh <[email protected]>, 2013-2014 *) 3*9a0e4156SSadaf Ebrahimi 4*9a0e4156SSadaf Ebrahimiopen Arm64_const 5*9a0e4156SSadaf Ebrahimi 6*9a0e4156SSadaf Ebrahimi(* architecture specific info of instruction *) 7*9a0e4156SSadaf Ebrahimitype arm64_op_shift = { 8*9a0e4156SSadaf Ebrahimi shift_type: int; 9*9a0e4156SSadaf Ebrahimi shift_value: int; 10*9a0e4156SSadaf Ebrahimi} 11*9a0e4156SSadaf Ebrahimi 12*9a0e4156SSadaf Ebrahimitype arm64_op_mem = { 13*9a0e4156SSadaf Ebrahimi base: int; 14*9a0e4156SSadaf Ebrahimi index: int; 15*9a0e4156SSadaf Ebrahimi disp: int 16*9a0e4156SSadaf Ebrahimi} 17*9a0e4156SSadaf Ebrahimi 18*9a0e4156SSadaf Ebrahimitype arm64_op_value = 19*9a0e4156SSadaf Ebrahimi | ARM64_OP_INVALID of int 20*9a0e4156SSadaf Ebrahimi | ARM64_OP_REG of int 21*9a0e4156SSadaf Ebrahimi | ARM64_OP_CIMM of int 22*9a0e4156SSadaf Ebrahimi | ARM64_OP_IMM of int 23*9a0e4156SSadaf Ebrahimi | ARM64_OP_FP of float 24*9a0e4156SSadaf Ebrahimi | ARM64_OP_MEM of arm64_op_mem 25*9a0e4156SSadaf Ebrahimi | ARM64_OP_REG_MRS of int 26*9a0e4156SSadaf Ebrahimi | ARM64_OP_REG_MSR of int 27*9a0e4156SSadaf Ebrahimi | ARM64_OP_PSTATE of int 28*9a0e4156SSadaf Ebrahimi | ARM64_OP_SYS of int 29*9a0e4156SSadaf Ebrahimi | ARM64_OP_PREFETCH of int 30*9a0e4156SSadaf Ebrahimi | ARM64_OP_BARRIER of int 31*9a0e4156SSadaf Ebrahimi 32*9a0e4156SSadaf Ebrahimitype arm64_op = { 33*9a0e4156SSadaf Ebrahimi vector_index: int; 34*9a0e4156SSadaf Ebrahimi vas: int; 35*9a0e4156SSadaf Ebrahimi vess: int; 36*9a0e4156SSadaf Ebrahimi shift: arm64_op_shift; 37*9a0e4156SSadaf Ebrahimi ext: int; 38*9a0e4156SSadaf Ebrahimi value: arm64_op_value; 39*9a0e4156SSadaf Ebrahimi} 40*9a0e4156SSadaf Ebrahimi 41*9a0e4156SSadaf Ebrahimitype cs_arm64 = { 42*9a0e4156SSadaf Ebrahimi cc: int; 43*9a0e4156SSadaf Ebrahimi update_flags: bool; 44*9a0e4156SSadaf Ebrahimi writeback: bool; 45*9a0e4156SSadaf Ebrahimi operands: arm64_op array; 46*9a0e4156SSadaf Ebrahimi} 47