1*9a0e4156SSadaf Ebrahimi/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2*9a0e4156SSadaf Ebrahimi|* *| 3*9a0e4156SSadaf Ebrahimi|*Target Instruction Enum Values *| 4*9a0e4156SSadaf Ebrahimi|* *| 5*9a0e4156SSadaf Ebrahimi|* Automatically generated file, do not edit! *| 6*9a0e4156SSadaf Ebrahimi|* *| 7*9a0e4156SSadaf Ebrahimi\*===----------------------------------------------------------------------===*/ 8*9a0e4156SSadaf Ebrahimi 9*9a0e4156SSadaf Ebrahimi 10*9a0e4156SSadaf Ebrahimi#ifdef GET_INSTRINFO_ENUM 11*9a0e4156SSadaf Ebrahimi#undef GET_INSTRINFO_ENUM 12*9a0e4156SSadaf Ebrahimi 13*9a0e4156SSadaf Ebrahimienum { 14*9a0e4156SSadaf Ebrahimi TMS320C64x_PHI = 0, 15*9a0e4156SSadaf Ebrahimi TMS320C64x_INLINEASM = 1, 16*9a0e4156SSadaf Ebrahimi TMS320C64x_CFI_INSTRUCTION = 2, 17*9a0e4156SSadaf Ebrahimi TMS320C64x_EH_LABEL = 3, 18*9a0e4156SSadaf Ebrahimi TMS320C64x_GC_LABEL = 4, 19*9a0e4156SSadaf Ebrahimi TMS320C64x_KILL = 5, 20*9a0e4156SSadaf Ebrahimi TMS320C64x_EXTRACT_SUBREG = 6, 21*9a0e4156SSadaf Ebrahimi TMS320C64x_INSERT_SUBREG = 7, 22*9a0e4156SSadaf Ebrahimi TMS320C64x_IMPLICIT_DEF = 8, 23*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBREG_TO_REG = 9, 24*9a0e4156SSadaf Ebrahimi TMS320C64x_COPY_TO_REGCLASS = 10, 25*9a0e4156SSadaf Ebrahimi TMS320C64x_DBG_VALUE = 11, 26*9a0e4156SSadaf Ebrahimi TMS320C64x_REG_SEQUENCE = 12, 27*9a0e4156SSadaf Ebrahimi TMS320C64x_COPY = 13, 28*9a0e4156SSadaf Ebrahimi TMS320C64x_BUNDLE = 14, 29*9a0e4156SSadaf Ebrahimi TMS320C64x_LIFETIME_START = 15, 30*9a0e4156SSadaf Ebrahimi TMS320C64x_LIFETIME_END = 16, 31*9a0e4156SSadaf Ebrahimi TMS320C64x_STACKMAP = 17, 32*9a0e4156SSadaf Ebrahimi TMS320C64x_PATCHPOINT = 18, 33*9a0e4156SSadaf Ebrahimi TMS320C64x_LOAD_STACK_GUARD = 19, 34*9a0e4156SSadaf Ebrahimi TMS320C64x_STATEPOINT = 20, 35*9a0e4156SSadaf Ebrahimi TMS320C64x_FRAME_ALLOC = 21, 36*9a0e4156SSadaf Ebrahimi TMS320C64x_ABS2_l2_rr = 22, 37*9a0e4156SSadaf Ebrahimi TMS320C64x_ABS_l1_pp = 23, 38*9a0e4156SSadaf Ebrahimi TMS320C64x_ABS_l1_rr = 24, 39*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD2_d2_rrr = 25, 40*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD2_l1_rrr_x2 = 26, 41*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD2_s1_rrr = 27, 42*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD4_l1_rrr_x2 = 28, 43*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAB_d1_rir = 29, 44*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAB_d1_rrr = 30, 45*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAD_d1_rir = 31, 46*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAD_d1_rrr = 32, 47*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAH_d1_rir = 33, 48*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAH_d1_rrr = 34, 49*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAW_d1_rir = 35, 50*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDAW_d1_rrr = 36, 51*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDKPC_s3_iir = 37, 52*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDK_s2_ir = 38, 53*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDU_l1_rpp = 39, 54*9a0e4156SSadaf Ebrahimi TMS320C64x_ADDU_l1_rrp_x2 = 40, 55*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_d1_rir = 41, 56*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_d1_rrr = 42, 57*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_d2_rir = 43, 58*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_d2_rrr = 44, 59*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_l1_ipp = 45, 60*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_l1_irr = 46, 61*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_l1_rpp = 47, 62*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_l1_rrp_x2 = 48, 63*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_l1_rrr_x2 = 49, 64*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_s1_irr = 50, 65*9a0e4156SSadaf Ebrahimi TMS320C64x_ADD_s1_rrr = 51, 66*9a0e4156SSadaf Ebrahimi TMS320C64x_ANDN_d2_rrr = 52, 67*9a0e4156SSadaf Ebrahimi TMS320C64x_ANDN_l1_rrr_x2 = 53, 68*9a0e4156SSadaf Ebrahimi TMS320C64x_ANDN_s4_rrr = 54, 69*9a0e4156SSadaf Ebrahimi TMS320C64x_AND_d2_rir = 55, 70*9a0e4156SSadaf Ebrahimi TMS320C64x_AND_d2_rrr = 56, 71*9a0e4156SSadaf Ebrahimi TMS320C64x_AND_l1_irr = 57, 72*9a0e4156SSadaf Ebrahimi TMS320C64x_AND_l1_rrr_x2 = 58, 73*9a0e4156SSadaf Ebrahimi TMS320C64x_AND_s1_irr = 59, 74*9a0e4156SSadaf Ebrahimi TMS320C64x_AND_s1_rrr = 60, 75*9a0e4156SSadaf Ebrahimi TMS320C64x_AVG2_m1_rrr = 61, 76*9a0e4156SSadaf Ebrahimi TMS320C64x_AVGU4_m1_rrr = 62, 77*9a0e4156SSadaf Ebrahimi TMS320C64x_BDEC_s8_ir = 63, 78*9a0e4156SSadaf Ebrahimi TMS320C64x_BITC4_m2_rr = 64, 79*9a0e4156SSadaf Ebrahimi TMS320C64x_BNOP_s10_ri = 65, 80*9a0e4156SSadaf Ebrahimi TMS320C64x_BNOP_s9_ii = 66, 81*9a0e4156SSadaf Ebrahimi TMS320C64x_BPOS_s8_ir = 67, 82*9a0e4156SSadaf Ebrahimi TMS320C64x_B_s5_i = 68, 83*9a0e4156SSadaf Ebrahimi TMS320C64x_B_s6_r = 69, 84*9a0e4156SSadaf Ebrahimi TMS320C64x_B_s7_irp = 70, 85*9a0e4156SSadaf Ebrahimi TMS320C64x_B_s7_nrp = 71, 86*9a0e4156SSadaf Ebrahimi TMS320C64x_CLR_s15_riir = 72, 87*9a0e4156SSadaf Ebrahimi TMS320C64x_CLR_s1_rrr = 73, 88*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPEQ2_s1_rrr = 74, 89*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPEQ4_s1_rrr = 75, 90*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPEQ_l1_ipr = 76, 91*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPEQ_l1_irr = 77, 92*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPEQ_l1_rpr = 78, 93*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPEQ_l1_rrr_x2 = 79, 94*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPGT2_s1_rrr = 80, 95*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPGTU4_s1_rrr = 81, 96*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPGT_l1_ipr = 82, 97*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPGT_l1_irr = 83, 98*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPGT_l1_rpr = 84, 99*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPGT_l1_rrr_x2 = 85, 100*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLTU_l1_ipr = 86, 101*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLTU_l1_irr = 87, 102*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLTU_l1_rpr = 88, 103*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLTU_l1_rrr_x2 = 89, 104*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLT_l1_ipr = 90, 105*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLT_l1_irr = 91, 106*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLT_l1_rpr = 92, 107*9a0e4156SSadaf Ebrahimi TMS320C64x_CMPLT_l1_rrr_x2 = 93, 108*9a0e4156SSadaf Ebrahimi TMS320C64x_DEAL_m2_rr = 94, 109*9a0e4156SSadaf Ebrahimi TMS320C64x_DOTP2_m1_rrp = 95, 110*9a0e4156SSadaf Ebrahimi TMS320C64x_DOTP2_m1_rrr = 96, 111*9a0e4156SSadaf Ebrahimi TMS320C64x_DOTPN2_m1_rrr = 97, 112*9a0e4156SSadaf Ebrahimi TMS320C64x_DOTPNRSU2_m1_rrr = 98, 113*9a0e4156SSadaf Ebrahimi TMS320C64x_DOTPRSU2_m1_rrr = 99, 114*9a0e4156SSadaf Ebrahimi TMS320C64x_DOTPSU4_m1_rrr = 100, 115*9a0e4156SSadaf Ebrahimi TMS320C64x_DOTPU4_m1_rrr = 101, 116*9a0e4156SSadaf Ebrahimi TMS320C64x_EXTU_s15_riir = 102, 117*9a0e4156SSadaf Ebrahimi TMS320C64x_EXTU_s1_rrr = 103, 118*9a0e4156SSadaf Ebrahimi TMS320C64x_EXT_s15_riir = 104, 119*9a0e4156SSadaf Ebrahimi TMS320C64x_EXT_s1_rrr = 105, 120*9a0e4156SSadaf Ebrahimi TMS320C64x_GMPGTU_l1_ipr = 106, 121*9a0e4156SSadaf Ebrahimi TMS320C64x_GMPGTU_l1_irr = 107, 122*9a0e4156SSadaf Ebrahimi TMS320C64x_GMPGTU_l1_rpr = 108, 123*9a0e4156SSadaf Ebrahimi TMS320C64x_GMPGTU_l1_rrr_x2 = 109, 124*9a0e4156SSadaf Ebrahimi TMS320C64x_GMPY4_m1_rrr = 110, 125*9a0e4156SSadaf Ebrahimi TMS320C64x_LDBU_d5_mr = 111, 126*9a0e4156SSadaf Ebrahimi TMS320C64x_LDBU_d6_mr = 112, 127*9a0e4156SSadaf Ebrahimi TMS320C64x_LDB_d5_mr = 113, 128*9a0e4156SSadaf Ebrahimi TMS320C64x_LDB_d6_mr = 114, 129*9a0e4156SSadaf Ebrahimi TMS320C64x_LDDW_d7_mp = 115, 130*9a0e4156SSadaf Ebrahimi TMS320C64x_LDHU_d5_mr = 116, 131*9a0e4156SSadaf Ebrahimi TMS320C64x_LDHU_d6_mr = 117, 132*9a0e4156SSadaf Ebrahimi TMS320C64x_LDH_d5_mr = 118, 133*9a0e4156SSadaf Ebrahimi TMS320C64x_LDH_d6_mr = 119, 134*9a0e4156SSadaf Ebrahimi TMS320C64x_LDNDW_d8_mp = 120, 135*9a0e4156SSadaf Ebrahimi TMS320C64x_LDNW_d5_mr = 121, 136*9a0e4156SSadaf Ebrahimi TMS320C64x_LDW_d5_mr = 122, 137*9a0e4156SSadaf Ebrahimi TMS320C64x_LDW_d6_mr = 123, 138*9a0e4156SSadaf Ebrahimi TMS320C64x_LMBD_l1_irr = 124, 139*9a0e4156SSadaf Ebrahimi TMS320C64x_LMBD_l1_rrr_x2 = 125, 140*9a0e4156SSadaf Ebrahimi TMS320C64x_MAX2_l1_rrr_x2 = 126, 141*9a0e4156SSadaf Ebrahimi TMS320C64x_MAXU4_l1_rrr_x2 = 127, 142*9a0e4156SSadaf Ebrahimi TMS320C64x_MIN2_l1_rrr_x2 = 128, 143*9a0e4156SSadaf Ebrahimi TMS320C64x_MINU4_l1_rrr_x2 = 129, 144*9a0e4156SSadaf Ebrahimi TMS320C64x_MPY2_m1_rrp = 130, 145*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHIR_m1_rrr = 131, 146*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHI_m1_rrp = 132, 147*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHLU_m4_rrr = 133, 148*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHL_m4_rrr = 134, 149*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHSLU_m4_rrr = 135, 150*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHSU_m4_rrr = 136, 151*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHULS_m4_rrr = 137, 152*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHUS_m4_rrr = 138, 153*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYHU_m4_rrr = 139, 154*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYH_m4_rrr = 140, 155*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYLHU_m4_rrr = 141, 156*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYLH_m4_rrr = 142, 157*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYLIR_m1_rrr = 143, 158*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYLI_m1_rrp = 144, 159*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYLSHU_m4_rrr = 145, 160*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYLUHS_m4_rrr = 146, 161*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYSU4_m1_rrp = 147, 162*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYSU_m4_irr = 148, 163*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYSU_m4_rrr = 149, 164*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYU4_m1_rrp = 150, 165*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYUS_m4_rrr = 151, 166*9a0e4156SSadaf Ebrahimi TMS320C64x_MPYU_m4_rrr = 152, 167*9a0e4156SSadaf Ebrahimi TMS320C64x_MPY_m4_irr = 153, 168*9a0e4156SSadaf Ebrahimi TMS320C64x_MPY_m4_rrr = 154, 169*9a0e4156SSadaf Ebrahimi TMS320C64x_MVC_s1_rr = 155, 170*9a0e4156SSadaf Ebrahimi TMS320C64x_MVC_s1_rr2 = 156, 171*9a0e4156SSadaf Ebrahimi TMS320C64x_MVD_m2_rr = 157, 172*9a0e4156SSadaf Ebrahimi TMS320C64x_MVKLH_s12_ir = 158, 173*9a0e4156SSadaf Ebrahimi TMS320C64x_MVKL_s12_ir = 159, 174*9a0e4156SSadaf Ebrahimi TMS320C64x_MVK_d1_rr = 160, 175*9a0e4156SSadaf Ebrahimi TMS320C64x_MVK_l2_ir = 161, 176*9a0e4156SSadaf Ebrahimi TMS320C64x_NOP_n = 162, 177*9a0e4156SSadaf Ebrahimi TMS320C64x_NORM_l1_pr = 163, 178*9a0e4156SSadaf Ebrahimi TMS320C64x_NORM_l1_rr = 164, 179*9a0e4156SSadaf Ebrahimi TMS320C64x_OR_d2_rir = 165, 180*9a0e4156SSadaf Ebrahimi TMS320C64x_OR_d2_rrr = 166, 181*9a0e4156SSadaf Ebrahimi TMS320C64x_OR_l1_irr = 167, 182*9a0e4156SSadaf Ebrahimi TMS320C64x_OR_l1_rrr_x2 = 168, 183*9a0e4156SSadaf Ebrahimi TMS320C64x_OR_s1_irr = 169, 184*9a0e4156SSadaf Ebrahimi TMS320C64x_OR_s1_rrr = 170, 185*9a0e4156SSadaf Ebrahimi TMS320C64x_PACK2_l1_rrr_x2 = 171, 186*9a0e4156SSadaf Ebrahimi TMS320C64x_PACK2_s4_rrr = 172, 187*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKH2_l1_rrr_x2 = 173, 188*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKH2_s1_rrr = 174, 189*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKH4_l1_rrr_x2 = 175, 190*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKHL2_l1_rrr_x2 = 176, 191*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKHL2_s1_rrr = 177, 192*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKL4_l1_rrr_x2 = 178, 193*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKLH2_l1_rrr_x2 = 179, 194*9a0e4156SSadaf Ebrahimi TMS320C64x_PACKLH2_s1_rrr = 180, 195*9a0e4156SSadaf Ebrahimi TMS320C64x_ROTL_m1_rir = 181, 196*9a0e4156SSadaf Ebrahimi TMS320C64x_ROTL_m1_rrr = 182, 197*9a0e4156SSadaf Ebrahimi TMS320C64x_SADD2_s4_rrr = 183, 198*9a0e4156SSadaf Ebrahimi TMS320C64x_SADDU4_s4_rrr = 184, 199*9a0e4156SSadaf Ebrahimi TMS320C64x_SADDUS2_s4_rrr = 185, 200*9a0e4156SSadaf Ebrahimi TMS320C64x_SADD_l1_ipp = 186, 201*9a0e4156SSadaf Ebrahimi TMS320C64x_SADD_l1_irr = 187, 202*9a0e4156SSadaf Ebrahimi TMS320C64x_SADD_l1_rpp = 188, 203*9a0e4156SSadaf Ebrahimi TMS320C64x_SADD_l1_rrr_x2 = 189, 204*9a0e4156SSadaf Ebrahimi TMS320C64x_SADD_s1_rrr = 190, 205*9a0e4156SSadaf Ebrahimi TMS320C64x_SAT_l1_pr = 191, 206*9a0e4156SSadaf Ebrahimi TMS320C64x_SET_s15_riir = 192, 207*9a0e4156SSadaf Ebrahimi TMS320C64x_SET_s1_rrr = 193, 208*9a0e4156SSadaf Ebrahimi TMS320C64x_SHFL_m2_rr = 194, 209*9a0e4156SSadaf Ebrahimi TMS320C64x_SHLMB_l1_rrr_x2 = 195, 210*9a0e4156SSadaf Ebrahimi TMS320C64x_SHLMB_s4_rrr = 196, 211*9a0e4156SSadaf Ebrahimi TMS320C64x_SHL_s1_pip = 197, 212*9a0e4156SSadaf Ebrahimi TMS320C64x_SHL_s1_prp = 198, 213*9a0e4156SSadaf Ebrahimi TMS320C64x_SHL_s1_rip = 199, 214*9a0e4156SSadaf Ebrahimi TMS320C64x_SHL_s1_rir = 200, 215*9a0e4156SSadaf Ebrahimi TMS320C64x_SHL_s1_rrp = 201, 216*9a0e4156SSadaf Ebrahimi TMS320C64x_SHL_s1_rrr = 202, 217*9a0e4156SSadaf Ebrahimi TMS320C64x_SHR2_s1_rir = 203, 218*9a0e4156SSadaf Ebrahimi TMS320C64x_SHR2_s4_rrr = 204, 219*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRMB_l1_rrr_x2 = 205, 220*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRMB_s4_rrr = 206, 221*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRU2_s1_rir = 207, 222*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRU2_s4_rrr = 208, 223*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRU_s1_pip = 209, 224*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRU_s1_prp = 210, 225*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRU_s1_rir = 211, 226*9a0e4156SSadaf Ebrahimi TMS320C64x_SHRU_s1_rrr = 212, 227*9a0e4156SSadaf Ebrahimi TMS320C64x_SHR_s1_pip = 213, 228*9a0e4156SSadaf Ebrahimi TMS320C64x_SHR_s1_prp = 214, 229*9a0e4156SSadaf Ebrahimi TMS320C64x_SHR_s1_rir = 215, 230*9a0e4156SSadaf Ebrahimi TMS320C64x_SHR_s1_rrr = 216, 231*9a0e4156SSadaf Ebrahimi TMS320C64x_SMPY2_m1_rrp = 217, 232*9a0e4156SSadaf Ebrahimi TMS320C64x_SMPYHL_m4_rrr = 218, 233*9a0e4156SSadaf Ebrahimi TMS320C64x_SMPYH_m4_rrr = 219, 234*9a0e4156SSadaf Ebrahimi TMS320C64x_SMPYLH_m4_rrr = 220, 235*9a0e4156SSadaf Ebrahimi TMS320C64x_SMPY_m4_rrr = 221, 236*9a0e4156SSadaf Ebrahimi TMS320C64x_SPACK2_s4_rrr = 222, 237*9a0e4156SSadaf Ebrahimi TMS320C64x_SPACKU4_s4_rrr = 223, 238*9a0e4156SSadaf Ebrahimi TMS320C64x_SSHL_s1_rir = 224, 239*9a0e4156SSadaf Ebrahimi TMS320C64x_SSHL_s1_rrr = 225, 240*9a0e4156SSadaf Ebrahimi TMS320C64x_SSHVL_m1_rrr = 226, 241*9a0e4156SSadaf Ebrahimi TMS320C64x_SSHVR_m1_rrr = 227, 242*9a0e4156SSadaf Ebrahimi TMS320C64x_SSUB_l1_ipp = 228, 243*9a0e4156SSadaf Ebrahimi TMS320C64x_SSUB_l1_irr = 229, 244*9a0e4156SSadaf Ebrahimi TMS320C64x_SSUB_l1_rrr_x1 = 230, 245*9a0e4156SSadaf Ebrahimi TMS320C64x_SSUB_l1_rrr_x2 = 231, 246*9a0e4156SSadaf Ebrahimi TMS320C64x_STB_d5_rm = 232, 247*9a0e4156SSadaf Ebrahimi TMS320C64x_STB_d6_rm = 233, 248*9a0e4156SSadaf Ebrahimi TMS320C64x_STDW_d7_pm = 234, 249*9a0e4156SSadaf Ebrahimi TMS320C64x_STH_d5_rm = 235, 250*9a0e4156SSadaf Ebrahimi TMS320C64x_STH_d6_rm = 236, 251*9a0e4156SSadaf Ebrahimi TMS320C64x_STNDW_d8_pm = 237, 252*9a0e4156SSadaf Ebrahimi TMS320C64x_STNW_d5_rm = 238, 253*9a0e4156SSadaf Ebrahimi TMS320C64x_STW_d5_rm = 239, 254*9a0e4156SSadaf Ebrahimi TMS320C64x_STW_d6_rm = 240, 255*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB2_d2_rrr = 241, 256*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB2_l1_rrr_x2 = 242, 257*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB2_s1_rrr = 243, 258*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB4_l1_rrr_x2 = 244, 259*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBABS4_l1_rrr_x2 = 245, 260*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBAB_d1_rir = 246, 261*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBAB_d1_rrr = 247, 262*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBAH_d1_rir = 248, 263*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBAH_d1_rrr = 249, 264*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBAW_d1_rir = 250, 265*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBAW_d1_rrr = 251, 266*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBC_l1_rrr_x2 = 252, 267*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBU_l1_rrp_x1 = 253, 268*9a0e4156SSadaf Ebrahimi TMS320C64x_SUBU_l1_rrp_x2 = 254, 269*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_d1_rir = 255, 270*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_d1_rrr = 256, 271*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_d2_rrr = 257, 272*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_l1_ipp = 258, 273*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_l1_irr = 259, 274*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_l1_rrp_x1 = 260, 275*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_l1_rrp_x2 = 261, 276*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_l1_rrr_x1 = 262, 277*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_l1_rrr_x2 = 263, 278*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_s1_irr = 264, 279*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_s1_rrr = 265, 280*9a0e4156SSadaf Ebrahimi TMS320C64x_SUB_s4_rrr = 266, 281*9a0e4156SSadaf Ebrahimi TMS320C64x_SWAP4_l2_rr = 267, 282*9a0e4156SSadaf Ebrahimi TMS320C64x_UNPKHU4_l2_rr = 268, 283*9a0e4156SSadaf Ebrahimi TMS320C64x_UNPKHU4_s14_rr = 269, 284*9a0e4156SSadaf Ebrahimi TMS320C64x_UNPKLU4_l2_rr = 270, 285*9a0e4156SSadaf Ebrahimi TMS320C64x_UNPKLU4_s14_rr = 271, 286*9a0e4156SSadaf Ebrahimi TMS320C64x_XOR_d2_rir = 272, 287*9a0e4156SSadaf Ebrahimi TMS320C64x_XOR_d2_rrr = 273, 288*9a0e4156SSadaf Ebrahimi TMS320C64x_XOR_l1_irr = 274, 289*9a0e4156SSadaf Ebrahimi TMS320C64x_XOR_l1_rrr_x2 = 275, 290*9a0e4156SSadaf Ebrahimi TMS320C64x_XOR_s1_irr = 276, 291*9a0e4156SSadaf Ebrahimi TMS320C64x_XOR_s1_rrr = 277, 292*9a0e4156SSadaf Ebrahimi TMS320C64x_XPND2_m2_rr = 278, 293*9a0e4156SSadaf Ebrahimi TMS320C64x_XPND4_m2_rr = 279, 294*9a0e4156SSadaf Ebrahimi TMS320C64x_INSTRUCTION_LIST_END = 280 295*9a0e4156SSadaf Ebrahimi}; 296*9a0e4156SSadaf Ebrahimi 297*9a0e4156SSadaf Ebrahimi#endif // GET_INSTRINFO_ENUM 298*9a0e4156SSadaf Ebrahimi 299