1*9a0e4156SSadaf Ebrahimi //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===// 2*9a0e4156SSadaf Ebrahimi // 3*9a0e4156SSadaf Ebrahimi // The LLVM Compiler Infrastructure 4*9a0e4156SSadaf Ebrahimi // 5*9a0e4156SSadaf Ebrahimi // This file is distributed under the University of Illinois Open Source 6*9a0e4156SSadaf Ebrahimi // License. See LICENSE.TXT for details. 7*9a0e4156SSadaf Ebrahimi // 8*9a0e4156SSadaf Ebrahimi //===----------------------------------------------------------------------===// 9*9a0e4156SSadaf Ebrahimi 10*9a0e4156SSadaf Ebrahimi /* Capstone Disassembly Engine */ 11*9a0e4156SSadaf Ebrahimi /* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */ 12*9a0e4156SSadaf Ebrahimi 13*9a0e4156SSadaf Ebrahimi #ifndef CS_SYSTEMZMCTARGETDESC_H 14*9a0e4156SSadaf Ebrahimi #define CS_SYSTEMZMCTARGETDESC_H 15*9a0e4156SSadaf Ebrahimi 16*9a0e4156SSadaf Ebrahimi // Maps of asm register numbers to LLVM register numbers, with 0 indicating 17*9a0e4156SSadaf Ebrahimi // an invalid register. In principle we could use 32-bit and 64-bit register 18*9a0e4156SSadaf Ebrahimi // classes directly, provided that we relegated the GPR allocation order 19*9a0e4156SSadaf Ebrahimi // in SystemZRegisterInfo.td to an AltOrder and left the default order 20*9a0e4156SSadaf Ebrahimi // as %r0-%r15. It seems better to provide the same interface for 21*9a0e4156SSadaf Ebrahimi // all classes though. 22*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_GR32Regs[16]; 23*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_GRH32Regs[16]; 24*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_GR64Regs[16]; 25*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_GR128Regs[16]; 26*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_FP32Regs[16]; 27*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_FP64Regs[16]; 28*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_FP128Regs[16]; 29*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_VR32Regs[32]; 30*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_VR64Regs[32]; 31*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_VR128Regs[32]; 32*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_AR32Regs[16]; 33*9a0e4156SSadaf Ebrahimi extern const unsigned SystemZMC_CR64Regs[16]; 34*9a0e4156SSadaf Ebrahimi 35*9a0e4156SSadaf Ebrahimi // Return the 0-based number of the first architectural register that 36*9a0e4156SSadaf Ebrahimi // contains the given LLVM register. E.g. R1D -> 1. 37*9a0e4156SSadaf Ebrahimi unsigned SystemZMC_getFirstReg(unsigned Reg); 38*9a0e4156SSadaf Ebrahimi 39*9a0e4156SSadaf Ebrahimi // Defines symbolic names for SystemZ registers. 40*9a0e4156SSadaf Ebrahimi // This defines a mapping from register name to register number. 41*9a0e4156SSadaf Ebrahimi //#define GET_REGINFO_ENUM 42*9a0e4156SSadaf Ebrahimi //#include "SystemZGenRegisterInfo.inc" 43*9a0e4156SSadaf Ebrahimi 44*9a0e4156SSadaf Ebrahimi // Defines symbolic names for the SystemZ instructions. 45*9a0e4156SSadaf Ebrahimi //#define GET_INSTRINFO_ENUM 46*9a0e4156SSadaf Ebrahimi //#include "SystemZGenInstrInfo.inc" 47*9a0e4156SSadaf Ebrahimi 48*9a0e4156SSadaf Ebrahimi //#define GET_SUBTARGETINFO_ENUM 49*9a0e4156SSadaf Ebrahimi //#include "SystemZGenSubtargetInfo.inc" 50*9a0e4156SSadaf Ebrahimi 51*9a0e4156SSadaf Ebrahimi #endif 52