1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <assert.h>
8*54fd6939SJiyong Park #include <stdint.h>
9*54fd6939SJiyong Park
10*54fd6939SJiyong Park #include <common/debug.h>
11*54fd6939SJiyong Park #include <common/runtime_svc.h>
12*54fd6939SJiyong Park #include <services/pci_svc.h>
13*54fd6939SJiyong Park #include <services/std_svc.h>
14*54fd6939SJiyong Park #include <smccc_helpers.h>
15*54fd6939SJiyong Park
validate_rw_addr_sz(uint32_t addr,uint64_t off,uint64_t sz)16*54fd6939SJiyong Park static uint64_t validate_rw_addr_sz(uint32_t addr, uint64_t off, uint64_t sz)
17*54fd6939SJiyong Park {
18*54fd6939SJiyong Park uint32_t nseg;
19*54fd6939SJiyong Park uint32_t ret;
20*54fd6939SJiyong Park uint32_t start_end_bus;
21*54fd6939SJiyong Park
22*54fd6939SJiyong Park ret = pci_get_bus_for_seg(PCI_ADDR_SEG(addr), &start_end_bus, &nseg);
23*54fd6939SJiyong Park
24*54fd6939SJiyong Park if (ret != SMC_PCI_CALL_SUCCESS) {
25*54fd6939SJiyong Park return SMC_PCI_CALL_INVAL_PARAM;
26*54fd6939SJiyong Park }
27*54fd6939SJiyong Park switch (sz) {
28*54fd6939SJiyong Park case SMC_PCI_SZ_8BIT:
29*54fd6939SJiyong Park case SMC_PCI_SZ_16BIT:
30*54fd6939SJiyong Park case SMC_PCI_SZ_32BIT:
31*54fd6939SJiyong Park break;
32*54fd6939SJiyong Park default:
33*54fd6939SJiyong Park return SMC_PCI_CALL_INVAL_PARAM;
34*54fd6939SJiyong Park }
35*54fd6939SJiyong Park if ((off + sz) > (PCI_OFFSET_MASK + 1U)) {
36*54fd6939SJiyong Park return SMC_PCI_CALL_INVAL_PARAM;
37*54fd6939SJiyong Park }
38*54fd6939SJiyong Park return SMC_PCI_CALL_SUCCESS;
39*54fd6939SJiyong Park }
40*54fd6939SJiyong Park
pci_smc_handler(uint32_t smc_fid,u_register_t x1,u_register_t x2,u_register_t x3,u_register_t x4,void * cookie,void * handle,u_register_t flags)41*54fd6939SJiyong Park uint64_t pci_smc_handler(uint32_t smc_fid,
42*54fd6939SJiyong Park u_register_t x1,
43*54fd6939SJiyong Park u_register_t x2,
44*54fd6939SJiyong Park u_register_t x3,
45*54fd6939SJiyong Park u_register_t x4,
46*54fd6939SJiyong Park void *cookie,
47*54fd6939SJiyong Park void *handle,
48*54fd6939SJiyong Park u_register_t flags)
49*54fd6939SJiyong Park {
50*54fd6939SJiyong Park switch (smc_fid) {
51*54fd6939SJiyong Park case SMC_PCI_VERSION: {
52*54fd6939SJiyong Park pcie_version ver;
53*54fd6939SJiyong Park
54*54fd6939SJiyong Park ver.major = 1U;
55*54fd6939SJiyong Park ver.minor = 0U;
56*54fd6939SJiyong Park SMC_RET4(handle, ver.val, 0U, 0U, 0U);
57*54fd6939SJiyong Park }
58*54fd6939SJiyong Park case SMC_PCI_FEATURES:
59*54fd6939SJiyong Park switch (x1) {
60*54fd6939SJiyong Park case SMC_PCI_VERSION:
61*54fd6939SJiyong Park case SMC_PCI_FEATURES:
62*54fd6939SJiyong Park case SMC_PCI_READ:
63*54fd6939SJiyong Park case SMC_PCI_WRITE:
64*54fd6939SJiyong Park case SMC_PCI_SEG_INFO:
65*54fd6939SJiyong Park SMC_RET1(handle, SMC_PCI_CALL_SUCCESS);
66*54fd6939SJiyong Park default:
67*54fd6939SJiyong Park SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
68*54fd6939SJiyong Park }
69*54fd6939SJiyong Park break;
70*54fd6939SJiyong Park case SMC_PCI_READ: {
71*54fd6939SJiyong Park uint32_t ret;
72*54fd6939SJiyong Park
73*54fd6939SJiyong Park if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
74*54fd6939SJiyong Park SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
75*54fd6939SJiyong Park }
76*54fd6939SJiyong Park if (x4 != 0U) {
77*54fd6939SJiyong Park SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
78*54fd6939SJiyong Park }
79*54fd6939SJiyong Park if (pci_read_config(x1, x2, x3, &ret) != 0U) {
80*54fd6939SJiyong Park SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
81*54fd6939SJiyong Park } else {
82*54fd6939SJiyong Park SMC_RET2(handle, SMC_PCI_CALL_SUCCESS, ret);
83*54fd6939SJiyong Park }
84*54fd6939SJiyong Park break;
85*54fd6939SJiyong Park }
86*54fd6939SJiyong Park case SMC_PCI_WRITE: {
87*54fd6939SJiyong Park uint32_t ret;
88*54fd6939SJiyong Park
89*54fd6939SJiyong Park if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
90*54fd6939SJiyong Park SMC_RET1(handle, SMC_PCI_CALL_INVAL_PARAM);
91*54fd6939SJiyong Park }
92*54fd6939SJiyong Park ret = pci_write_config(x1, x2, x3, x4);
93*54fd6939SJiyong Park SMC_RET1(handle, ret);
94*54fd6939SJiyong Park break;
95*54fd6939SJiyong Park }
96*54fd6939SJiyong Park case SMC_PCI_SEG_INFO: {
97*54fd6939SJiyong Park uint32_t nseg;
98*54fd6939SJiyong Park uint32_t ret;
99*54fd6939SJiyong Park uint32_t start_end_bus;
100*54fd6939SJiyong Park
101*54fd6939SJiyong Park if ((x2 != 0U) || (x3 != 0U) || (x4 != 0U)) {
102*54fd6939SJiyong Park SMC_RET3(handle, SMC_PCI_CALL_INVAL_PARAM, 0U, 0U);
103*54fd6939SJiyong Park }
104*54fd6939SJiyong Park ret = pci_get_bus_for_seg(x1, &start_end_bus, &nseg);
105*54fd6939SJiyong Park SMC_RET3(handle, ret, start_end_bus, nseg);
106*54fd6939SJiyong Park break;
107*54fd6939SJiyong Park }
108*54fd6939SJiyong Park default:
109*54fd6939SJiyong Park /* should be unreachable */
110*54fd6939SJiyong Park WARN("Unimplemented PCI Service Call: 0x%x\n", smc_fid);
111*54fd6939SJiyong Park SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
112*54fd6939SJiyong Park }
113*54fd6939SJiyong Park }
114