1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <assert_macros.S> 10*54fd6939SJiyong Park#include <platform_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park .global sq_calc_core_pos 13*54fd6939SJiyong Park .global plat_my_core_pos 14*54fd6939SJiyong Park .global platform_mem_init 15*54fd6939SJiyong Park .global plat_is_my_cpu_primary 16*54fd6939SJiyong Park .global plat_secondary_cold_boot_setup 17*54fd6939SJiyong Park .global plat_crash_console_init 18*54fd6939SJiyong Park .global plat_crash_console_putc 19*54fd6939SJiyong Park .global plat_crash_console_flush 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park/* 22*54fd6939SJiyong Park * unsigned int sq_calc_core_pos(u_register_t mpidr) 23*54fd6939SJiyong Park * core_pos = (cluster_id * max_cpus_per_cluster) + core_id 24*54fd6939SJiyong Park */ 25*54fd6939SJiyong Parkfunc sq_calc_core_pos 26*54fd6939SJiyong Park and x1, x0, #MPIDR_CPU_MASK 27*54fd6939SJiyong Park and x0, x0, #MPIDR_CLUSTER_MASK 28*54fd6939SJiyong Park add x0, x1, x0, lsr #7 29*54fd6939SJiyong Park ret 30*54fd6939SJiyong Parkendfunc sq_calc_core_pos 31*54fd6939SJiyong Park 32*54fd6939SJiyong Parkfunc plat_my_core_pos 33*54fd6939SJiyong Park mrs x0, mpidr_el1 34*54fd6939SJiyong Park b sq_calc_core_pos 35*54fd6939SJiyong Parkendfunc plat_my_core_pos 36*54fd6939SJiyong Park 37*54fd6939SJiyong Parkfunc platform_mem_init 38*54fd6939SJiyong Park ret 39*54fd6939SJiyong Parkendfunc platform_mem_init 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park/* 42*54fd6939SJiyong Park * Secondary CPUs are placed in a holding pen, waiting for their mailbox 43*54fd6939SJiyong Park * to be populated. Note that all CPUs share the same mailbox ; therefore, 44*54fd6939SJiyong Park * populating it will release all CPUs from their holding pen. If 45*54fd6939SJiyong Park * finer-grained control is needed then this should be handled in the 46*54fd6939SJiyong Park * code that secondary CPUs jump to. 47*54fd6939SJiyong Park */ 48*54fd6939SJiyong Parkfunc plat_secondary_cold_boot_setup 49*54fd6939SJiyong Park ldr x0, sq_sec_entrypoint 50*54fd6939SJiyong Park 51*54fd6939SJiyong Park /* Wait until the mailbox gets populated */ 52*54fd6939SJiyong Parkpoll_mailbox: 53*54fd6939SJiyong Park cbz x0, 1f 54*54fd6939SJiyong Park br x0 55*54fd6939SJiyong Park1: 56*54fd6939SJiyong Park wfe 57*54fd6939SJiyong Park b poll_mailbox 58*54fd6939SJiyong Parkendfunc plat_secondary_cold_boot_setup 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park/* 61*54fd6939SJiyong Park * Find out whether the current cpu is the primary 62*54fd6939SJiyong Park * cpu (applicable only after a cold boot) 63*54fd6939SJiyong Park */ 64*54fd6939SJiyong Parkfunc plat_is_my_cpu_primary 65*54fd6939SJiyong Park mov x9, x30 66*54fd6939SJiyong Park bl plat_my_core_pos 67*54fd6939SJiyong Park ldr x1, =SQ_BOOT_CFG_ADDR 68*54fd6939SJiyong Park ldr x1, [x1] 69*54fd6939SJiyong Park ubfx x1, x1, #PLAT_SQ_PRIMARY_CPU_SHIFT, \ 70*54fd6939SJiyong Park #PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 71*54fd6939SJiyong Park cmp x0, x1 72*54fd6939SJiyong Park cset w0, eq 73*54fd6939SJiyong Park ret x9 74*54fd6939SJiyong Parkendfunc plat_is_my_cpu_primary 75*54fd6939SJiyong Park 76*54fd6939SJiyong Park/* 77*54fd6939SJiyong Park * int plat_crash_console_init(void) 78*54fd6939SJiyong Park * Function to initialize the crash console 79*54fd6939SJiyong Park * without a C Runtime to print crash report. 80*54fd6939SJiyong Park * Clobber list : x0, x1, x2 81*54fd6939SJiyong Park */ 82*54fd6939SJiyong Parkfunc plat_crash_console_init 83*54fd6939SJiyong Park mov_imm x0, PLAT_SQ_BOOT_UART_BASE 84*54fd6939SJiyong Park mov_imm x1, PLAT_SQ_BOOT_UART_CLK_IN_HZ 85*54fd6939SJiyong Park mov_imm x2, SQ_CONSOLE_BAUDRATE 86*54fd6939SJiyong Park b console_pl011_core_init 87*54fd6939SJiyong Parkendfunc plat_crash_console_init 88*54fd6939SJiyong Park 89*54fd6939SJiyong Park/* 90*54fd6939SJiyong Park * int plat_crash_console_putc(int c) 91*54fd6939SJiyong Park * Function to print a character on the crash 92*54fd6939SJiyong Park * console without a C Runtime. 93*54fd6939SJiyong Park * Clobber list : x1, x2 94*54fd6939SJiyong Park */ 95*54fd6939SJiyong Parkfunc plat_crash_console_putc 96*54fd6939SJiyong Park mov_imm x1, PLAT_SQ_BOOT_UART_BASE 97*54fd6939SJiyong Park b console_pl011_core_putc 98*54fd6939SJiyong Parkendfunc plat_crash_console_putc 99*54fd6939SJiyong Park 100*54fd6939SJiyong Park/* 101*54fd6939SJiyong Park * void plat_crash_console_flush(int c) 102*54fd6939SJiyong Park * Function to force a write of all buffered 103*54fd6939SJiyong Park * data that hasn't been output. 104*54fd6939SJiyong Park * Out : void. 105*54fd6939SJiyong Park * Clobber list : x0, x1 106*54fd6939SJiyong Park */ 107*54fd6939SJiyong Parkfunc plat_crash_console_flush 108*54fd6939SJiyong Park mov_imm x0, PLAT_SQ_BOOT_UART_BASE 109*54fd6939SJiyong Park b console_pl011_core_flush 110*54fd6939SJiyong Parkendfunc plat_crash_console_flush 111