1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#ifndef SYNQUACER_PLAT_LD_S__ 8*54fd6939SJiyong Park#define SYNQUACER_PLAT_LD_S__ 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park#include <lib/xlat_tables/xlat_tables_defs.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park#define SPM_SHIM_EXCEPTIONS_VMA SP_DRAM 13*54fd6939SJiyong Park 14*54fd6939SJiyong ParkMEMORY { 15*54fd6939SJiyong Park SP_DRAM (rw): ORIGIN = PLAT_SQ_SP_PRIV_BASE, LENGTH = PLAT_SQ_SP_PRIV_SIZE 16*54fd6939SJiyong Park} 17*54fd6939SJiyong Park 18*54fd6939SJiyong ParkSECTIONS 19*54fd6939SJiyong Park{ 20*54fd6939SJiyong Park /* 21*54fd6939SJiyong Park * Put the page tables in secure DRAM so that the PTW can make cacheable 22*54fd6939SJiyong Park * accesses, as the core SPM code expects. (The SRAM on SynQuacer does 23*54fd6939SJiyong Park * not support inner shareable WBWA mappings so it is mapped normal 24*54fd6939SJiyong Park * non-cacheable) 25*54fd6939SJiyong Park */ 26*54fd6939SJiyong Park sp_xlat_table (NOLOAD) : ALIGN(PAGE_SIZE) { 27*54fd6939SJiyong Park *(sp_xlat_table) 28*54fd6939SJiyong Park } >SP_DRAM 29*54fd6939SJiyong Park} 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park#endif /* SYNQUACER_PLAT_LD_S__ */ 32