1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef RK3399_DEF_H 8*54fd6939SJiyong Park #define RK3399_DEF_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <addressmap.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park #define RK3399_PRIMARY_CPU 0x0 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park /* Special value used to verify platform parameters from BL2 to BL3-1 */ 15*54fd6939SJiyong Park #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park /************************************************************************** 18*54fd6939SJiyong Park * UART related constants 19*54fd6939SJiyong Park **************************************************************************/ 20*54fd6939SJiyong Park #define RK3399_BAUDRATE 115200 21*54fd6939SJiyong Park #define RK3399_UART_CLOCK 24000000 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park /****************************************************************************** 24*54fd6939SJiyong Park * System counter frequency related constants 25*54fd6939SJiyong Park ******************************************************************************/ 26*54fd6939SJiyong Park #define SYS_COUNTER_FREQ_IN_TICKS 24000000 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park /* Base rockchip_platform compatible GIC memory map */ 29*54fd6939SJiyong Park #define BASE_GICD_BASE (GIC500_BASE) 30*54fd6939SJiyong Park #define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park /***************************************************************************** 33*54fd6939SJiyong Park * CCI-400 related constants 34*54fd6939SJiyong Park ******************************************************************************/ 35*54fd6939SJiyong Park #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 36*54fd6939SJiyong Park #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park /****************************************************************************** 39*54fd6939SJiyong Park * sgi, ppi 40*54fd6939SJiyong Park ******************************************************************************/ 41*54fd6939SJiyong Park #define ARM_IRQ_SEC_PHY_TIMER 29 42*54fd6939SJiyong Park 43*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_0 8 44*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_1 9 45*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_2 10 46*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_3 11 47*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_4 12 48*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_5 13 49*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_6 14 50*54fd6939SJiyong Park #define ARM_IRQ_SEC_SGI_7 15 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park /* 53*54fd6939SJiyong Park * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 54*54fd6939SJiyong Park * terminology. On a GICv2 system or mode, the lists will be merged and treated 55*54fd6939SJiyong Park * as Group 0 interrupts. 56*54fd6939SJiyong Park */ 57*54fd6939SJiyong Park #define PLAT_RK_GICV3_G1S_IRQS \ 58*54fd6939SJiyong Park INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 59*54fd6939SJiyong Park INTR_GROUP1S, GIC_INTR_CFG_LEVEL) 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park #define PLAT_RK_GICV3_G0_IRQS \ 62*54fd6939SJiyong Park INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 63*54fd6939SJiyong Park INTR_GROUP0, GIC_INTR_CFG_LEVEL) 64*54fd6939SJiyong Park 65*54fd6939SJiyong Park #endif /* RK3399_DEF_H */ 66