1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef RK3368_DEF_H 8*54fd6939SJiyong Park #define RK3368_DEF_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park /* Special value used to verify platform parameters from BL2 to BL3-1 */ 11*54fd6939SJiyong Park #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #define CCI400_BASE 0xffb90000 14*54fd6939SJiyong Park #define CCI400_SIZE 0x10000 15*54fd6939SJiyong Park 16*54fd6939SJiyong Park #define GIC400_BASE 0xffb70000 17*54fd6939SJiyong Park #define GIC400_SIZE 0x10000 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park #define STIME_BASE 0xff830000 20*54fd6939SJiyong Park #define STIME_SIZE 0x10000 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park #define CRU_BASE 0xff760000 23*54fd6939SJiyong Park #define CRU_SIZE 0x10000 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park #define GRF_BASE 0xff770000 26*54fd6939SJiyong Park #define GRF_SIZE 0x10000 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park #define SGRF_BASE 0xff740000 29*54fd6939SJiyong Park #define SGRF_SIZE 0x10000 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park #define PMU_BASE 0xff730000 32*54fd6939SJiyong Park #define PMU_GRF_BASE 0xff738000 33*54fd6939SJiyong Park #define PMU_SIZE 0x10000 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park #define RK_INTMEM_BASE 0xff8c0000 36*54fd6939SJiyong Park #define RK_INTMEM_SIZE 0x10000 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park #define UART0_BASE 0xff180000 39*54fd6939SJiyong Park #define UART0_SIZE 0x10000 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park #define UART1_BASE 0xff190000 42*54fd6939SJiyong Park #define UART1_SIZE 0x10000 43*54fd6939SJiyong Park 44*54fd6939SJiyong Park #define UART2_BASE 0xff690000 45*54fd6939SJiyong Park #define UART2_SIZE 0x10000 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park #define UART3_BASE 0xff1b0000 48*54fd6939SJiyong Park #define UART3_SIZE 0x10000 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park #define UART4_BASE 0xff1c0000 51*54fd6939SJiyong Park #define UART4_SIZE 0x10000 52*54fd6939SJiyong Park 53*54fd6939SJiyong Park #define CRU_BASE 0xff760000 54*54fd6939SJiyong Park 55*54fd6939SJiyong Park #define PMUSRAM_BASE 0xff720000 56*54fd6939SJiyong Park #define PMUSRAM_SIZE 0x10000 57*54fd6939SJiyong Park #define PMUSRAM_RSIZE 0x1000 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park #define DDR_PCTL_BASE 0xff610000 60*54fd6939SJiyong Park #define DDR_PCTL_SIZE 0x10000 61*54fd6939SJiyong Park 62*54fd6939SJiyong Park #define DDR_PHY_BASE 0xff620000 63*54fd6939SJiyong Park #define DDR_PHY_SIZE 0x10000 64*54fd6939SJiyong Park 65*54fd6939SJiyong Park #define SERVICE_BUS_BASE 0xffac0000 66*54fd6939SJiyong Park #define SERVICE_BUS_SISE 0x50000 67*54fd6939SJiyong Park 68*54fd6939SJiyong Park #define COLD_BOOT_BASE 0xffff0000 69*54fd6939SJiyong Park /************************************************************************** 70*54fd6939SJiyong Park * UART related constants 71*54fd6939SJiyong Park **************************************************************************/ 72*54fd6939SJiyong Park #define RK3368_BAUDRATE 115200 73*54fd6939SJiyong Park #define RK3368_UART_CLOCK 24000000 74*54fd6939SJiyong Park 75*54fd6939SJiyong Park /****************************************************************************** 76*54fd6939SJiyong Park * System counter frequency related constants 77*54fd6939SJiyong Park ******************************************************************************/ 78*54fd6939SJiyong Park #define SYS_COUNTER_FREQ_IN_TICKS 24000000 79*54fd6939SJiyong Park 80*54fd6939SJiyong Park /****************************************************************************** 81*54fd6939SJiyong Park * GIC-400 & interrupt handling related constants 82*54fd6939SJiyong Park ******************************************************************************/ 83*54fd6939SJiyong Park 84*54fd6939SJiyong Park /* Base rk_platform compatible GIC memory map */ 85*54fd6939SJiyong Park #define RK3368_GICD_BASE (GIC400_BASE + 0x1000) 86*54fd6939SJiyong Park #define RK3368_GICC_BASE (GIC400_BASE + 0x2000) 87*54fd6939SJiyong Park #define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */ 88*54fd6939SJiyong Park 89*54fd6939SJiyong Park /***************************************************************************** 90*54fd6939SJiyong Park * CCI-400 related constants 91*54fd6939SJiyong Park ******************************************************************************/ 92*54fd6939SJiyong Park #define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3 93*54fd6939SJiyong Park #define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4 94*54fd6939SJiyong Park 95*54fd6939SJiyong Park /****************************************************************************** 96*54fd6939SJiyong Park * sgi, ppi 97*54fd6939SJiyong Park ******************************************************************************/ 98*54fd6939SJiyong Park #define RK_IRQ_SEC_PHY_TIMER 29 99*54fd6939SJiyong Park 100*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_0 8 101*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_1 9 102*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_2 10 103*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_3 11 104*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_4 12 105*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_5 13 106*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_6 14 107*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_7 15 108*54fd6939SJiyong Park 109*54fd6939SJiyong Park /* 110*54fd6939SJiyong Park * Define a list of Group 0 interrupts. 111*54fd6939SJiyong Park */ 112*54fd6939SJiyong Park #define PLAT_RK_GICV2_G0_IRQS \ 113*54fd6939SJiyong Park INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 114*54fd6939SJiyong Park GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) 115*54fd6939SJiyong Park 116*54fd6939SJiyong Park #endif /* RK3368_DEF_H */ 117