1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef RK3328_DEF_H 8*54fd6939SJiyong Park #define RK3328_DEF_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #define MAJOR_VERSION (1) 11*54fd6939SJiyong Park #define MINOR_VERSION (2) 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #define SIZE_K(n) ((n) * 1024) 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park /* Special value used to verify platform parameters from BL2 to BL3-1 */ 16*54fd6939SJiyong Park #define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park #define UART0_BASE 0xff110000 19*54fd6939SJiyong Park #define UART0_SIZE SIZE_K(64) 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park #define UART1_BASE 0xff120000 22*54fd6939SJiyong Park #define UART1_SIZE SIZE_K(64) 23*54fd6939SJiyong Park 24*54fd6939SJiyong Park #define UART2_BASE 0xff130000 25*54fd6939SJiyong Park #define UART2_SIZE SIZE_K(64) 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park #define PMU_BASE 0xff140000 28*54fd6939SJiyong Park #define PMU_SIZE SIZE_K(64) 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park #define SGRF_BASE 0xff0d0000 31*54fd6939SJiyong Park #define SGRF_SIZE SIZE_K(64) 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park #define CRU_BASE 0xff440000 34*54fd6939SJiyong Park #define CRU_SIZE SIZE_K(64) 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park #define GRF_BASE 0xff100000 37*54fd6939SJiyong Park #define GRF_SIZE SIZE_K(64) 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park #define GPIO0_BASE 0xff210000 40*54fd6939SJiyong Park #define GPIO0_SIZE SIZE_K(32) 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park #define GPIO1_BASE 0xff220000 43*54fd6939SJiyong Park #define GPIO1_SIZE SIZE_K(32) 44*54fd6939SJiyong Park 45*54fd6939SJiyong Park #define GPIO2_BASE 0xff230000 46*54fd6939SJiyong Park #define GPIO2_SIZE SIZE_K(64) 47*54fd6939SJiyong Park 48*54fd6939SJiyong Park #define GPIO3_BASE 0xff240000 49*54fd6939SJiyong Park #define GPIO3_SIZE SIZE_K(64) 50*54fd6939SJiyong Park 51*54fd6939SJiyong Park #define STIME_BASE 0xff1d0000 52*54fd6939SJiyong Park #define STIME_SIZE SIZE_K(64) 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park #define INTMEM_BASE 0xff090000 55*54fd6939SJiyong Park #define INTMEM_SIZE SIZE_K(32) 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park #define SRAM_LDS_BASE (INTMEM_BASE + SIZE_K(4)) 58*54fd6939SJiyong Park #define SRAM_LDS_SIZE (INTMEM_SIZE - SIZE_K(4)) 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park #define PMUSRAM_BASE INTMEM_BASE 61*54fd6939SJiyong Park #define PMUSRAM_SIZE SIZE_K(4) 62*54fd6939SJiyong Park #define PMUSRAM_RSIZE SIZE_K(4) 63*54fd6939SJiyong Park 64*54fd6939SJiyong Park #define VOP_BASE 0xff370000 65*54fd6939SJiyong Park #define VOP_SIZE SIZE_K(16) 66*54fd6939SJiyong Park 67*54fd6939SJiyong Park #define DDR_PHY_BASE 0xff400000 68*54fd6939SJiyong Park #define DDR_PHY_SIZE SIZE_K(4) 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park #define SERVER_MSCH_BASE 0xff720000 71*54fd6939SJiyong Park #define SERVER_MSCH_SIZE SIZE_K(4) 72*54fd6939SJiyong Park 73*54fd6939SJiyong Park #define DDR_UPCTL_BASE 0xff780000 74*54fd6939SJiyong Park #define DDR_UPCTL_SIZE SIZE_K(12) 75*54fd6939SJiyong Park 76*54fd6939SJiyong Park #define DDR_MONITOR_BASE 0xff790000 77*54fd6939SJiyong Park #define DDR_MONITOR_SIZE SIZE_K(4) 78*54fd6939SJiyong Park 79*54fd6939SJiyong Park #define FIREWALL_DDR_BASE 0xff7c0000 80*54fd6939SJiyong Park #define FIREWALL_DDR_SIZE SIZE_K(64) 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park #define FIREWALL_CFG_BASE 0xff7d0000 83*54fd6939SJiyong Park #define FIREWALL_CFG_SIZE SIZE_K(64) 84*54fd6939SJiyong Park 85*54fd6939SJiyong Park #define GIC400_BASE 0xff810000 86*54fd6939SJiyong Park #define GIC400_SIZE SIZE_K(64) 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park #define DDR_GRF_BASE 0xff798000 89*54fd6939SJiyong Park #define DDR_GRF_SIZE SIZE_K(16) 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park #define PWM_BASE 0xff1b0000 92*54fd6939SJiyong Park #define PWM_SIZE SIZE_K(64) 93*54fd6939SJiyong Park 94*54fd6939SJiyong Park #define DDR_PARAM_BASE 0x02000000 95*54fd6939SJiyong Park #define DDR_PARAM_SIZE SIZE_K(4) 96*54fd6939SJiyong Park 97*54fd6939SJiyong Park #define EFUSE8_BASE 0xff260000 98*54fd6939SJiyong Park #define EFUSE8_SIZE SIZE_K(4) 99*54fd6939SJiyong Park 100*54fd6939SJiyong Park #define EFUSE32_BASE 0xff0b0000 101*54fd6939SJiyong Park #define EFUSE32_SIZE SIZE_K(4) 102*54fd6939SJiyong Park 103*54fd6939SJiyong Park /************************************************************************** 104*54fd6939SJiyong Park * UART related constants 105*54fd6939SJiyong Park **************************************************************************/ 106*54fd6939SJiyong Park #define RK3328_BAUDRATE 1500000 107*54fd6939SJiyong Park #define RK3328_UART_CLOCK 24000000 108*54fd6939SJiyong Park 109*54fd6939SJiyong Park /****************************************************************************** 110*54fd6939SJiyong Park * System counter frequency related constants 111*54fd6939SJiyong Park ******************************************************************************/ 112*54fd6939SJiyong Park #define SYS_COUNTER_FREQ_IN_TICKS 24000000U 113*54fd6939SJiyong Park #define SYS_COUNTER_FREQ_IN_MHZ 24 114*54fd6939SJiyong Park 115*54fd6939SJiyong Park /****************************************************************************** 116*54fd6939SJiyong Park * GIC-400 & interrupt handling related constants 117*54fd6939SJiyong Park ******************************************************************************/ 118*54fd6939SJiyong Park 119*54fd6939SJiyong Park /* Base rk_platform compatible GIC memory map */ 120*54fd6939SJiyong Park #define RK3328_GICD_BASE (GIC400_BASE + 0x1000) 121*54fd6939SJiyong Park #define RK3328_GICC_BASE (GIC400_BASE + 0x2000) 122*54fd6939SJiyong Park #define RK3328_GICR_BASE 0 /* no GICR in GIC-400 */ 123*54fd6939SJiyong Park 124*54fd6939SJiyong Park /****************************************************************************** 125*54fd6939SJiyong Park * sgi, ppi 126*54fd6939SJiyong Park ******************************************************************************/ 127*54fd6939SJiyong Park #define RK_IRQ_SEC_PHY_TIMER 29 128*54fd6939SJiyong Park 129*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_0 8 130*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_1 9 131*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_2 10 132*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_3 11 133*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_4 12 134*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_5 13 135*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_6 14 136*54fd6939SJiyong Park #define RK_IRQ_SEC_SGI_7 15 137*54fd6939SJiyong Park 138*54fd6939SJiyong Park /* 139*54fd6939SJiyong Park * Define a list of Group 0 interrupts. 140*54fd6939SJiyong Park */ 141*54fd6939SJiyong Park #define PLAT_RK_GICV2_G0_IRQS \ 142*54fd6939SJiyong Park INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ 143*54fd6939SJiyong Park GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \ 144*54fd6939SJiyong Park INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ 145*54fd6939SJiyong Park GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL) 146*54fd6939SJiyong Park 147*54fd6939SJiyong Park #define SHARE_MEM_BASE 0x100000/* [1MB, 1MB+60K]*/ 148*54fd6939SJiyong Park #define SHARE_MEM_PAGE_NUM 15 149*54fd6939SJiyong Park #define SHARE_MEM_SIZE SIZE_K(SHARE_MEM_PAGE_NUM * 4) 150*54fd6939SJiyong Park 151*54fd6939SJiyong Park #endif /* RK3328_DEF_H */ 152