xref: /aosp_15_r20/external/arm-trusted-firmware/plat/rockchip/px30/include/plat.ld.S (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park/*
2*54fd6939SJiyong Park * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park#ifndef __ROCKCHIP_PLAT_LD_S__
8*54fd6939SJiyong Park#define __ROCKCHIP_PLAT_LD_S__
9*54fd6939SJiyong Park
10*54fd6939SJiyong ParkMEMORY {
11*54fd6939SJiyong Park    PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
12*54fd6939SJiyong Park}
13*54fd6939SJiyong Park
14*54fd6939SJiyong ParkSECTIONS
15*54fd6939SJiyong Park{
16*54fd6939SJiyong Park	. = PMUSRAM_BASE;
17*54fd6939SJiyong Park
18*54fd6939SJiyong Park	/*
19*54fd6939SJiyong Park	 * pmu_cpuson_entrypoint request address
20*54fd6939SJiyong Park	 * align 64K when resume, so put it in the
21*54fd6939SJiyong Park	 * start of pmusram
22*54fd6939SJiyong Park	 */
23*54fd6939SJiyong Park	.pmusram : {
24*54fd6939SJiyong Park		ASSERT(. == ALIGN(64 * 1024),
25*54fd6939SJiyong Park			".pmusram.entry request 64K aligned.");
26*54fd6939SJiyong Park		KEEP(*(.pmusram.entry))
27*54fd6939SJiyong Park
28*54fd6939SJiyong Park		__bl31_pmusram_text_start = .;
29*54fd6939SJiyong Park		*(.pmusram.text)
30*54fd6939SJiyong Park		*(.pmusram.rodata)
31*54fd6939SJiyong Park		__bl31_pmusram_text_end = .;
32*54fd6939SJiyong Park		__bl31_pmusram_data_start = .;
33*54fd6939SJiyong Park		*(.pmusram.data)
34*54fd6939SJiyong Park		__bl31_pmusram_data_end = .;
35*54fd6939SJiyong Park	} >PMUSRAM
36*54fd6939SJiyong Park}
37*54fd6939SJiyong Park
38*54fd6939SJiyong Park#endif /* __ROCKCHIP_PLAT_LD_S__ */
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