1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #include <platform_def.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park #include <common/bl_common.h> 10*54fd6939SJiyong Park #include <common/interrupt_props.h> 11*54fd6939SJiyong Park #include <drivers/arm/gicv3.h> 12*54fd6939SJiyong Park #include <lib/utils.h> 13*54fd6939SJiyong Park #include <plat/common/platform.h> 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park /****************************************************************************** 16*54fd6939SJiyong Park * The following functions are defined as weak to allow a platform to override 17*54fd6939SJiyong Park * the way the GICv3 driver is initialised and used. 18*54fd6939SJiyong Park *****************************************************************************/ 19*54fd6939SJiyong Park #pragma weak plat_rockchip_gic_driver_init 20*54fd6939SJiyong Park #pragma weak plat_rockchip_gic_init 21*54fd6939SJiyong Park #pragma weak plat_rockchip_gic_cpuif_enable 22*54fd6939SJiyong Park #pragma weak plat_rockchip_gic_cpuif_disable 23*54fd6939SJiyong Park #pragma weak plat_rockchip_gic_pcpu_init 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park /* The GICv3 driver only needs to be initialized in EL3 */ 26*54fd6939SJiyong Park uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park static const interrupt_prop_t g01s_interrupt_props[] = { 29*54fd6939SJiyong Park PLAT_RK_GICV3_G0_IRQS, 30*54fd6939SJiyong Park PLAT_RK_GICV3_G1S_IRQS 31*54fd6939SJiyong Park }; 32*54fd6939SJiyong Park plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)33*54fd6939SJiyong Parkstatic unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr) 34*54fd6939SJiyong Park { 35*54fd6939SJiyong Park return (unsigned int)plat_core_pos_by_mpidr(mpidr); 36*54fd6939SJiyong Park } 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park const gicv3_driver_data_t rockchip_gic_data = { 39*54fd6939SJiyong Park .gicd_base = PLAT_RK_GICD_BASE, 40*54fd6939SJiyong Park .gicr_base = PLAT_RK_GICR_BASE, 41*54fd6939SJiyong Park .interrupt_props = g01s_interrupt_props, 42*54fd6939SJiyong Park .interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props), 43*54fd6939SJiyong Park .rdistif_num = PLATFORM_CORE_COUNT, 44*54fd6939SJiyong Park .rdistif_base_addrs = rdistif_base_addrs, 45*54fd6939SJiyong Park .mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos, 46*54fd6939SJiyong Park }; 47*54fd6939SJiyong Park plat_rockchip_gic_driver_init(void)48*54fd6939SJiyong Parkvoid plat_rockchip_gic_driver_init(void) 49*54fd6939SJiyong Park { 50*54fd6939SJiyong Park /* 51*54fd6939SJiyong Park * The GICv3 driver is initialized in EL3 and does not need 52*54fd6939SJiyong Park * to be initialized again in SEL1. This is because the S-EL1 53*54fd6939SJiyong Park * can use GIC system registers to manage interrupts and does 54*54fd6939SJiyong Park * not need GIC interface base addresses to be configured. 55*54fd6939SJiyong Park */ 56*54fd6939SJiyong Park #ifdef IMAGE_BL31 57*54fd6939SJiyong Park gicv3_driver_init(&rockchip_gic_data); 58*54fd6939SJiyong Park #endif 59*54fd6939SJiyong Park } 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park /****************************************************************************** 62*54fd6939SJiyong Park * RockChip common helper to initialize the GIC. Only invoked 63*54fd6939SJiyong Park * by BL31 64*54fd6939SJiyong Park *****************************************************************************/ plat_rockchip_gic_init(void)65*54fd6939SJiyong Parkvoid plat_rockchip_gic_init(void) 66*54fd6939SJiyong Park { 67*54fd6939SJiyong Park gicv3_distif_init(); 68*54fd6939SJiyong Park gicv3_rdistif_init(plat_my_core_pos()); 69*54fd6939SJiyong Park gicv3_cpuif_enable(plat_my_core_pos()); 70*54fd6939SJiyong Park } 71*54fd6939SJiyong Park 72*54fd6939SJiyong Park /****************************************************************************** 73*54fd6939SJiyong Park * RockChip common helper to enable the GIC CPU interface 74*54fd6939SJiyong Park *****************************************************************************/ plat_rockchip_gic_cpuif_enable(void)75*54fd6939SJiyong Parkvoid plat_rockchip_gic_cpuif_enable(void) 76*54fd6939SJiyong Park { 77*54fd6939SJiyong Park gicv3_cpuif_enable(plat_my_core_pos()); 78*54fd6939SJiyong Park } 79*54fd6939SJiyong Park 80*54fd6939SJiyong Park /****************************************************************************** 81*54fd6939SJiyong Park * RockChip common helper to disable the GIC CPU interface 82*54fd6939SJiyong Park *****************************************************************************/ plat_rockchip_gic_cpuif_disable(void)83*54fd6939SJiyong Parkvoid plat_rockchip_gic_cpuif_disable(void) 84*54fd6939SJiyong Park { 85*54fd6939SJiyong Park gicv3_cpuif_disable(plat_my_core_pos()); 86*54fd6939SJiyong Park } 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park /****************************************************************************** 89*54fd6939SJiyong Park * RockChip common helper to initialize the per-cpu redistributor interface 90*54fd6939SJiyong Park * in GICv3 91*54fd6939SJiyong Park *****************************************************************************/ plat_rockchip_gic_pcpu_init(void)92*54fd6939SJiyong Parkvoid plat_rockchip_gic_pcpu_init(void) 93*54fd6939SJiyong Park { 94*54fd6939SJiyong Park gicv3_rdistif_init(plat_my_core_pos()); 95*54fd6939SJiyong Park } 96