1*54fd6939SJiyong Park# 2*54fd6939SJiyong Park# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc. 3*54fd6939SJiyong Park# Copyright 2017-2020 NXP Semiconductors 4*54fd6939SJiyong Park# 5*54fd6939SJiyong Park# SPDX-License-Identifier: BSD-3-Clause 6*54fd6939SJiyong Park# 7*54fd6939SJiyong Park# 8*54fd6939SJiyong Park#------------------------------------------------------------------------------ 9*54fd6939SJiyong Park# 10*54fd6939SJiyong Park# This file contains the basic architecture definitions that drive the build 11*54fd6939SJiyong Park# 12*54fd6939SJiyong Park# ----------------------------------------------------------------------------- 13*54fd6939SJiyong Park 14*54fd6939SJiyong ParkCORE_TYPE := a72 15*54fd6939SJiyong Park 16*54fd6939SJiyong ParkCACHE_LINE := 6 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park# set to GIC400 or GIC500 19*54fd6939SJiyong ParkGIC := GIC500 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park# set to CCI400 or CCN504 or CCN508 22*54fd6939SJiyong ParkINTERCONNECT := CCN508 23*54fd6939SJiyong Park 24*54fd6939SJiyong Park# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 25*54fd6939SJiyong ParkCHASSIS := 3_2 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park# TZC IP Details TZC used is TZC380 or TZC400 28*54fd6939SJiyong ParkTZC_ID := TZC400 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park# CONSOLE Details available is NS16550 or PL011 31*54fd6939SJiyong ParkCONSOLE := PL011 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park# Select the DDR PHY generation to be used 34*54fd6939SJiyong ParkPLAT_DDR_PHY := PHY_GEN2 35*54fd6939SJiyong Park 36*54fd6939SJiyong ParkPHYS_SYS := 64 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park# Area of OCRAM reserved by ROM code 39*54fd6939SJiyong ParkNXP_ROM_RSVD := 0xa000 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 42*54fd6939SJiyong Park# Input to CST create_hdr_esbc tool 43*54fd6939SJiyong ParkCSF_HDR_SZ := 0x3000 44*54fd6939SJiyong Park 45*54fd6939SJiyong ParkNXP_SFP_VER := 3_4 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park# In IMAGE_BL2, compile time flag for handling Cache coherency 48*54fd6939SJiyong Park# with CAAM for BL2 running from OCRAM 49*54fd6939SJiyong ParkSEC_MEM_NON_COHERENT := yes 50*54fd6939SJiyong Park 51*54fd6939SJiyong Park# Defining the endianness for NXP ESDHC 52*54fd6939SJiyong ParkNXP_ESDHC_ENDIANNESS := LE 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park# Defining the endianness for NXP SFP 55*54fd6939SJiyong ParkNXP_SFP_ENDIANNESS := LE 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park# Defining the endianness for NXP GPIO 58*54fd6939SJiyong ParkNXP_GPIO_ENDIANNESS := LE 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park# Defining the endianness for NXP SNVS 61*54fd6939SJiyong ParkNXP_SNVS_ENDIANNESS := LE 62*54fd6939SJiyong Park 63*54fd6939SJiyong Park# Defining the endianness for NXP CCSR GUR register 64*54fd6939SJiyong ParkNXP_GUR_ENDIANNESS := LE 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park# Defining the endianness for NXP FSPI register 67*54fd6939SJiyong ParkNXP_FSPI_ENDIANNESS := LE 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park# Defining the endianness for NXP SEC 70*54fd6939SJiyong ParkNXP_SEC_ENDIANNESS := LE 71*54fd6939SJiyong Park 72*54fd6939SJiyong Park# Defining the endianness for NXP DDR 73*54fd6939SJiyong ParkNXP_DDR_ENDIANNESS := LE 74*54fd6939SJiyong Park 75*54fd6939SJiyong ParkNXP_DDR_INTLV_256B := 1 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park# OCRAM MAP for BL2 78*54fd6939SJiyong Park# Before BL2 79*54fd6939SJiyong Park# 0x18000000 - 0x18009fff -> Used by ROM code 80*54fd6939SJiyong Park# 0x1800a000 - 0x1800dfff -> CSF header for BL2 81*54fd6939SJiyong Park# (The above area i.e 0x18000000 - 0x1800dfff is available 82*54fd6939SJiyong Park# for DDR PHY images scratch pad region during BL2 run time) 83*54fd6939SJiyong Park# For FlexSPI boot 84*54fd6939SJiyong Park# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary 85*54fd6939SJiyong Park# For SD boot 86*54fd6939SJiyong Park# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary 87*54fd6939SJiyong Park# 0x18030000 - 0x18040000 -> Reserved for SD buffer 88*54fd6939SJiyong ParkOCRAM_START_ADDR := 0x18000000 89*54fd6939SJiyong ParkOCRAM_SIZE := 0x40000 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park# Location of BL2 on OCRAM 92*54fd6939SJiyong ParkBL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) 93*54fd6939SJiyong Park# Covert to HEX to be used by create_pbl.mk 94*54fd6939SJiyong ParkBL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) 95*54fd6939SJiyong Park 96*54fd6939SJiyong Park# BL2_HDR_LOC is at (OCRAM_ADDR + NXP_ROM_RSVD) 97*54fd6939SJiyong Park# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE 98*54fd6939SJiyong ParkBL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) ))) 99*54fd6939SJiyong Park# Covert to HEX to be used by create_pbl.mk 100*54fd6939SJiyong ParkBL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc) 101*54fd6939SJiyong Park 102*54fd6939SJiyong Park# SoC ERRATAS to be enabled 103*54fd6939SJiyong Park# 104*54fd6939SJiyong Park# Core Errata 105*54fd6939SJiyong ParkERRATA_A72_859971 := 1 106*54fd6939SJiyong Park 107*54fd6939SJiyong Park# SoC Errata 108*54fd6939SJiyong ParkERRATA_SOC_A050426 := 1 109*54fd6939SJiyong Park 110*54fd6939SJiyong Park# enable dynamic memory mapping 111*54fd6939SJiyong ParkPLAT_XLAT_TABLES_DYNAMIC := 1 112