1*54fd6939SJiyong Park# 2*54fd6939SJiyong Park# Copyright 2018-2021 NXP 3*54fd6939SJiyong Park# 4*54fd6939SJiyong Park# SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park# 6*54fd6939SJiyong Park# 7*54fd6939SJiyong Park#------------------------------------------------------------------------------ 8*54fd6939SJiyong Park# 9*54fd6939SJiyong Park# This file contains the basic architecture definitions that drive the build 10*54fd6939SJiyong Park# 11*54fd6939SJiyong Park# ----------------------------------------------------------------------------- 12*54fd6939SJiyong Park 13*54fd6939SJiyong ParkCORE_TYPE := a72 14*54fd6939SJiyong Park 15*54fd6939SJiyong ParkCACHE_LINE := 6 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park# Set to GIC400 or GIC500 18*54fd6939SJiyong ParkGIC := GIC500 19*54fd6939SJiyong Park 20*54fd6939SJiyong Park# Set to CCI400 or CCN504 or CCN508 21*54fd6939SJiyong ParkINTERCONNECT := CCI400 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park# Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2 24*54fd6939SJiyong ParkCHASSIS := 3_2 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park# TZC used is TZC380 or TZC400 27*54fd6939SJiyong ParkTZC_ID := TZC400 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park# CONSOLE is NS16550 or PL011 30*54fd6939SJiyong ParkCONSOLE := NS16550 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park# DDR PHY generation to be used 33*54fd6939SJiyong ParkPLAT_DDR_PHY := PHY_GEN1 34*54fd6939SJiyong Park 35*54fd6939SJiyong ParkPHYS_SYS := 64 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def 38*54fd6939SJiyong Park# Input to CST create_hdr_esbc tool 39*54fd6939SJiyong ParkCSF_HDR_SZ := 0x3000 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park# In IMAGE_BL2, compile time flag for handling Cache coherency 42*54fd6939SJiyong Park# with CAAM for BL2 running from OCRAM 43*54fd6939SJiyong ParkSEC_MEM_NON_COHERENT := yes 44*54fd6939SJiyong Park 45*54fd6939SJiyong Park# OCRAM MAP for BL2 46*54fd6939SJiyong Park# Before BL2 47*54fd6939SJiyong Park# 0x18000000 - 0x18009fff -> Used by ROM code 48*54fd6939SJiyong Park# 0x1800a000 - 0x1800dfff -> CSF header for BL2 49*54fd6939SJiyong Park# For FlexSFlexSPI boot 50*54fd6939SJiyong Park# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary 51*54fd6939SJiyong Park# For SD boot 52*54fd6939SJiyong Park# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary 53*54fd6939SJiyong Park# 0x18030000 - 0x18040000 -> Reserved for SD buffer 54*54fd6939SJiyong ParkOCRAM_START_ADDR := 0x18000000 55*54fd6939SJiyong ParkOCRAM_SIZE := 0x40000 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park# Area of OCRAM reserved by ROM code 58*54fd6939SJiyong ParkNXP_ROM_RSVD := 0xa000 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park# Location of BL2 on OCRAM 61*54fd6939SJiyong ParkBL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) ))) 62*54fd6939SJiyong Park 63*54fd6939SJiyong Park# Covert to HEX to be used by create_pbl.mk 64*54fd6939SJiyong ParkBL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc)) 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park# BL2_HDR_LOC is at (BL2_BASE + NXP_ROM_RSVD) 67*54fd6939SJiyong Park# This value BL2_HDR_LOC + CSF_HDR_SZ should not 68*54fd6939SJiyong Park# overalp with BL2_BASE 69*54fd6939SJiyong Park# Input to CST create_hdr_isbc tool 70*54fd6939SJiyong ParkBL2_HDR_LOC := 0x1800A000 71*54fd6939SJiyong Park 72*54fd6939SJiyong Park# SoC ERRATAS to be enabled 73*54fd6939SJiyong ParkERRATA_SOC_A008850 := 1 74*54fd6939SJiyong Park 75*54fd6939SJiyong ParkERRATA_DDR_A009803 := 1 76*54fd6939SJiyong ParkERRATA_DDR_A009942 := 1 77*54fd6939SJiyong ParkERRATA_DDR_A010165 := 1 78*54fd6939SJiyong Park 79*54fd6939SJiyong Park# Enable dynamic memory mapping 80*54fd6939SJiyong ParkPLAT_XLAT_TABLES_DYNAMIC := 1 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park# Define Endianness of each module 83*54fd6939SJiyong ParkNXP_GUR_ENDIANNESS := LE 84*54fd6939SJiyong ParkNXP_DDR_ENDIANNESS := LE 85*54fd6939SJiyong ParkNXP_SEC_ENDIANNESS := LE 86*54fd6939SJiyong ParkNXP_SFP_ENDIANNESS := LE 87*54fd6939SJiyong ParkNXP_SNVS_ENDIANNESS := LE 88*54fd6939SJiyong ParkNXP_ESDHC_ENDIANNESS := LE 89*54fd6939SJiyong ParkNXP_QSPI_ENDIANNESS := LE 90*54fd6939SJiyong ParkNXP_FSPI_ENDIANNESS := LE 91*54fd6939SJiyong ParkNXP_SCFG_ENDIANNESS := LE 92*54fd6939SJiyong ParkNXP_GPIO_ENDIANNESS := LE 93*54fd6939SJiyong Park 94*54fd6939SJiyong ParkNXP_SFP_VER := 3_4 95*54fd6939SJiyong Park 96*54fd6939SJiyong Park# OCRAM ECC Enabled 97*54fd6939SJiyong ParkOCRAM_ECC_EN := yes 98