1*54fd6939SJiyong Park# 2*54fd6939SJiyong Park# Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park# 4*54fd6939SJiyong Park# SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park# 6*54fd6939SJiyong Park 7*54fd6939SJiyong ParkMTK_PLAT := plat/mediatek 8*54fd6939SJiyong ParkMTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park# Add OEM customized codes 11*54fd6939SJiyong ParkOEMS := true 12*54fd6939SJiyong ParkMTK_SIP_KERNEL_BOOT_ENABLE := 1 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park 15*54fd6939SJiyong Parkifneq (${OEMS},none) 16*54fd6939SJiyong Park OEMS_INCLUDES := -I${MTK_PLAT}/common/custom/ 17*54fd6939SJiyong Park OEMS_SOURCES := ${MTK_PLAT}/common/custom/oem_svc.c 18*54fd6939SJiyong Parkendif 19*54fd6939SJiyong Park 20*54fd6939SJiyong ParkPLAT_INCLUDES := -I${MTK_PLAT}/common/ \ 21*54fd6939SJiyong Park -I${MTK_PLAT}/common/drivers/uart \ 22*54fd6939SJiyong Park -I${MTK_PLAT_SOC}/ \ 23*54fd6939SJiyong Park -I${MTK_PLAT_SOC}/drivers/timer/ \ 24*54fd6939SJiyong Park -I${MTK_PLAT_SOC}/include/ \ 25*54fd6939SJiyong Park -Iinclude/plat/arm/common/ \ 26*54fd6939SJiyong Park ${OEMS_INCLUDES} 27*54fd6939SJiyong Park 28*54fd6939SJiyong ParkPLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \ 29*54fd6939SJiyong Park lib/xlat_tables/xlat_tables_common.c \ 30*54fd6939SJiyong Park plat/common/plat_gic.c 31*54fd6939SJiyong Park 32*54fd6939SJiyong ParkBL31_SOURCES += drivers/arm/cci/cci.c \ 33*54fd6939SJiyong Park drivers/delay_timer/generic_delay_timer.c \ 34*54fd6939SJiyong Park drivers/arm/gic/common/gic_common.c \ 35*54fd6939SJiyong Park drivers/arm/gic/v2/gicv2_main.c \ 36*54fd6939SJiyong Park drivers/arm/gic/v2/gicv2_helpers.c \ 37*54fd6939SJiyong Park plat/common/plat_gicv2.c \ 38*54fd6939SJiyong Park drivers/console/aarch64/console.S \ 39*54fd6939SJiyong Park drivers/delay_timer/delay_timer.c \ 40*54fd6939SJiyong Park lib/cpus/aarch64/cortex_a53.S \ 41*54fd6939SJiyong Park ${MTK_PLAT_SOC}/bl31_plat_setup.c \ 42*54fd6939SJiyong Park ${MTK_PLAT_SOC}/plat_mt_gic.c \ 43*54fd6939SJiyong Park ${MTK_PLAT}/common/mtk_sip_svc.c \ 44*54fd6939SJiyong Park ${MTK_PLAT}/common/mtk_plat_common.c \ 45*54fd6939SJiyong Park ${MTK_PLAT}/common/drivers/uart/8250_console.S \ 46*54fd6939SJiyong Park ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ 47*54fd6939SJiyong Park ${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \ 48*54fd6939SJiyong Park ${MTK_PLAT_SOC}/plat_delay_timer.c \ 49*54fd6939SJiyong Park ${MTK_PLAT_SOC}/plat_pm.c \ 50*54fd6939SJiyong Park ${MTK_PLAT_SOC}/plat_topology.c \ 51*54fd6939SJiyong Park ${MTK_PLAT_SOC}/power_tracer.c \ 52*54fd6939SJiyong Park ${MTK_PLAT_SOC}/scu.c \ 53*54fd6939SJiyong Park ${OEMS_SOURCES} 54*54fd6939SJiyong Park 55*54fd6939SJiyong Park# Enable workarounds for selected Cortex-A53 erratas. 56*54fd6939SJiyong ParkERRATA_A53_826319 := 1 57*54fd6939SJiyong ParkERRATA_A53_836870 := 1 58*54fd6939SJiyong Park 59*54fd6939SJiyong ParkWORKAROUND_CVE_2017_5715 := 0 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park# indicate the reset vector address can be programmed 62*54fd6939SJiyong ParkPROGRAMMABLE_RESET_ADDRESS := 1 63*54fd6939SJiyong Park 64*54fd6939SJiyong Park$(eval $(call add_define,MTK_SIP_KERNEL_BOOT_ENABLE)) 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park# Do not enable SVE 67*54fd6939SJiyong ParkENABLE_SVE_FOR_NS := 0 68