1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef MCUCFG_H 8*54fd6939SJiyong Park #define MCUCFG_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <stdint.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park #include <platform_def.h> 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park struct mt6795_mcucfg_regs { 15*54fd6939SJiyong Park uint32_t mp0_ca7l_cache_config; 16*54fd6939SJiyong Park struct { 17*54fd6939SJiyong Park uint32_t mem_delsel0; 18*54fd6939SJiyong Park uint32_t mem_delsel1; 19*54fd6939SJiyong Park } mp0_cpu[4]; 20*54fd6939SJiyong Park uint32_t mp0_cache_mem_delsel0; 21*54fd6939SJiyong Park uint32_t mp0_cache_mem_delsel1; 22*54fd6939SJiyong Park uint32_t mp0_axi_config; 23*54fd6939SJiyong Park uint32_t mp0_misc_config[2]; 24*54fd6939SJiyong Park struct { 25*54fd6939SJiyong Park uint32_t rv_addr_lw; 26*54fd6939SJiyong Park uint32_t rv_addr_hw; 27*54fd6939SJiyong Park } mp0_rv_addr[4]; 28*54fd6939SJiyong Park uint32_t mp0_ca7l_cfg_dis; 29*54fd6939SJiyong Park uint32_t mp0_ca7l_clken_ctrl; 30*54fd6939SJiyong Park uint32_t mp0_ca7l_rst_ctrl; 31*54fd6939SJiyong Park uint32_t mp0_ca7l_misc_config; 32*54fd6939SJiyong Park uint32_t mp0_ca7l_dbg_pwr_ctrl; 33*54fd6939SJiyong Park uint32_t mp0_rw_rsvd0; 34*54fd6939SJiyong Park uint32_t mp0_rw_rsvd1; 35*54fd6939SJiyong Park uint32_t mp0_ro_rsvd; 36*54fd6939SJiyong Park uint32_t reserved0_0[100]; 37*54fd6939SJiyong Park uint32_t mp1_cpucfg; 38*54fd6939SJiyong Park uint32_t mp1_miscdbg; 39*54fd6939SJiyong Park uint32_t reserved0_1[13]; 40*54fd6939SJiyong Park uint32_t mp1_rst_ctl; 41*54fd6939SJiyong Park uint32_t mp1_clkenm_div; 42*54fd6939SJiyong Park uint32_t reserved0_2[7]; 43*54fd6939SJiyong Park uint32_t mp1_config_res; 44*54fd6939SJiyong Park uint32_t reserved0_3[13]; 45*54fd6939SJiyong Park struct { 46*54fd6939SJiyong Park uint32_t rv_addr_lw; 47*54fd6939SJiyong Park uint32_t rv_addr_hw; 48*54fd6939SJiyong Park } mp1_rv_addr[2]; 49*54fd6939SJiyong Park uint32_t reserved0_4[84]; 50*54fd6939SJiyong Park uint32_t mp0_rst_status; /* 0x400 */ 51*54fd6939SJiyong Park uint32_t mp0_dbg_ctrl; 52*54fd6939SJiyong Park uint32_t mp0_dbg_flag; 53*54fd6939SJiyong Park uint32_t mp0_ca7l_ir_mon; 54*54fd6939SJiyong Park struct { 55*54fd6939SJiyong Park uint32_t pc_lw; 56*54fd6939SJiyong Park uint32_t pc_hw; 57*54fd6939SJiyong Park uint32_t fp_arch32; 58*54fd6939SJiyong Park uint32_t sp_arch32; 59*54fd6939SJiyong Park uint32_t fp_arch64_lw; 60*54fd6939SJiyong Park uint32_t fp_arch64_hw; 61*54fd6939SJiyong Park uint32_t sp_arch64_lw; 62*54fd6939SJiyong Park uint32_t sp_arch64_hw; 63*54fd6939SJiyong Park } mp0_dbg_core[4]; 64*54fd6939SJiyong Park uint32_t dfd_ctrl; 65*54fd6939SJiyong Park uint32_t dfd_cnt_l; 66*54fd6939SJiyong Park uint32_t dfd_cnt_h; 67*54fd6939SJiyong Park uint32_t misccfg_mp0_rw_rsvd; 68*54fd6939SJiyong Park uint32_t misccfg_sec_vio_status0; 69*54fd6939SJiyong Park uint32_t misccfg_sec_vio_status1; 70*54fd6939SJiyong Park uint32_t reserved1[22]; 71*54fd6939SJiyong Park uint32_t misccfg_rw_rsvd; /* 0x500 */ 72*54fd6939SJiyong Park uint32_t mcusys_dbg_mon_sel_a; 73*54fd6939SJiyong Park uint32_t mcusys_dbg_mon; 74*54fd6939SJiyong Park uint32_t reserved2[61]; 75*54fd6939SJiyong Park uint32_t mcusys_config_a; /* 0x600 */ 76*54fd6939SJiyong Park uint32_t mcusys_config1_a; 77*54fd6939SJiyong Park uint32_t mcusys_gic_peribase_a; 78*54fd6939SJiyong Park uint32_t reserved3; 79*54fd6939SJiyong Park uint32_t sec_range0_start; /* 0x610 */ 80*54fd6939SJiyong Park uint32_t sec_range0_end; 81*54fd6939SJiyong Park uint32_t sec_range_enable; 82*54fd6939SJiyong Park uint32_t reserved4; 83*54fd6939SJiyong Park uint32_t int_pol_ctl[8]; /* 0x620 */ 84*54fd6939SJiyong Park uint32_t aclken_div; /* 0x640 */ 85*54fd6939SJiyong Park uint32_t pclken_div; 86*54fd6939SJiyong Park uint32_t l2c_sram_ctrl; 87*54fd6939SJiyong Park uint32_t armpll_jit_ctrl; 88*54fd6939SJiyong Park uint32_t cci_addrmap; /* 0x650 */ 89*54fd6939SJiyong Park uint32_t cci_config; 90*54fd6939SJiyong Park uint32_t cci_periphbase; 91*54fd6939SJiyong Park uint32_t cci_nevntcntovfl; 92*54fd6939SJiyong Park uint32_t cci_clk_ctrl; /* 0x660 */ 93*54fd6939SJiyong Park uint32_t cci_acel_s1_ctrl; 94*54fd6939SJiyong Park uint32_t bus_fabric_dcm_ctrl; 95*54fd6939SJiyong Park uint32_t reserved5; 96*54fd6939SJiyong Park uint32_t xgpt_ctl; /* 0x670 */ 97*54fd6939SJiyong Park uint32_t xgpt_idx; 98*54fd6939SJiyong Park uint32_t ptpod2_ctl0; 99*54fd6939SJiyong Park uint32_t ptpod2_ctl1; 100*54fd6939SJiyong Park uint32_t mcusys_revid; 101*54fd6939SJiyong Park uint32_t mcusys_rw_rsvd0; 102*54fd6939SJiyong Park uint32_t mcusys_rw_rsvd1; 103*54fd6939SJiyong Park }; 104*54fd6939SJiyong Park 105*54fd6939SJiyong Park static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE; 106*54fd6939SJiyong Park 107*54fd6939SJiyong Park /* cpu boot mode */ 108*54fd6939SJiyong Park #define MP0_CPUCFG_64BIT_SHIFT 12 109*54fd6939SJiyong Park #define MP1_CPUCFG_64BIT_SHIFT 28 110*54fd6939SJiyong Park #define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT) 111*54fd6939SJiyong Park #define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT) 112*54fd6939SJiyong Park 113*54fd6939SJiyong Park /* scu related */ 114*54fd6939SJiyong Park enum { 115*54fd6939SJiyong Park MP0_ACINACTM_SHIFT = 4, 116*54fd6939SJiyong Park MP1_ACINACTM_SHIFT = 0, 117*54fd6939SJiyong Park MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, 118*54fd6939SJiyong Park MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT 119*54fd6939SJiyong Park }; 120*54fd6939SJiyong Park 121*54fd6939SJiyong Park enum { 122*54fd6939SJiyong Park MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, 123*54fd6939SJiyong Park MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, 124*54fd6939SJiyong Park MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, 125*54fd6939SJiyong Park MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, 126*54fd6939SJiyong Park MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, 127*54fd6939SJiyong Park 128*54fd6939SJiyong Park MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = 129*54fd6939SJiyong Park 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, 130*54fd6939SJiyong Park MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = 131*54fd6939SJiyong Park 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, 132*54fd6939SJiyong Park MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = 133*54fd6939SJiyong Park 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, 134*54fd6939SJiyong Park MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = 135*54fd6939SJiyong Park 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, 136*54fd6939SJiyong Park MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = 137*54fd6939SJiyong Park 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT 138*54fd6939SJiyong Park }; 139*54fd6939SJiyong Park 140*54fd6939SJiyong Park enum { 141*54fd6939SJiyong Park MP1_AINACTS_SHIFT = 4, 142*54fd6939SJiyong Park MP1_AINACTS = 1 << MP1_AINACTS_SHIFT 143*54fd6939SJiyong Park }; 144*54fd6939SJiyong Park 145*54fd6939SJiyong Park enum { 146*54fd6939SJiyong Park MP1_SW_CG_GEN_SHIFT = 12, 147*54fd6939SJiyong Park MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT 148*54fd6939SJiyong Park }; 149*54fd6939SJiyong Park 150*54fd6939SJiyong Park enum { 151*54fd6939SJiyong Park MP1_L2RSTDISABLE_SHIFT = 14, 152*54fd6939SJiyong Park MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT 153*54fd6939SJiyong Park }; 154*54fd6939SJiyong Park 155*54fd6939SJiyong Park #endif /* MCUCFG_H */ 156