1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <common/bl_common.ld.h> 8*54fd6939SJiyong Park#include <lib/xlat_tables/xlat_tables_defs.h> 9*54fd6939SJiyong Park 10*54fd6939SJiyong ParkOUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 11*54fd6939SJiyong ParkOUTPUT_ARCH(PLATFORM_LINKER_ARCH) 12*54fd6939SJiyong ParkENTRY(bl31_entrypoint) 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park 15*54fd6939SJiyong ParkMEMORY { 16*54fd6939SJiyong Park RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_TZRAM_SIZE 17*54fd6939SJiyong Park RAM2 (rwx): ORIGIN = TZRAM2_BASE, LENGTH = TZRAM2_SIZE 18*54fd6939SJiyong Park} 19*54fd6939SJiyong Park 20*54fd6939SJiyong Park 21*54fd6939SJiyong ParkSECTIONS 22*54fd6939SJiyong Park{ 23*54fd6939SJiyong Park . = BL31_BASE; 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park ASSERT(. == ALIGN(2048), 26*54fd6939SJiyong Park "vector base is not aligned on a 2K boundary.") 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park __RO_START__ = .; 29*54fd6939SJiyong Park vector . : { 30*54fd6939SJiyong Park *(.vectors) 31*54fd6939SJiyong Park } >RAM 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park ASSERT(. == ALIGN(PAGE_SIZE), 34*54fd6939SJiyong Park "BL31_BASE address is not aligned on a page boundary.") 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park ro . : { 37*54fd6939SJiyong Park *bl31_entrypoint.o(.text*) 38*54fd6939SJiyong Park *(.text*) 39*54fd6939SJiyong Park *(.rodata*) 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park RODATA_COMMON 42*54fd6939SJiyong Park 43*54fd6939SJiyong Park __RO_END_UNALIGNED__ = .; 44*54fd6939SJiyong Park /* 45*54fd6939SJiyong Park * Memory page(s) mapped to this section will be marked as read-only, 46*54fd6939SJiyong Park * executable. No RW data from the next section must creep in. 47*54fd6939SJiyong Park * Ensure the rest of the current memory page is unused. 48*54fd6939SJiyong Park */ 49*54fd6939SJiyong Park . = ALIGN(PAGE_SIZE); 50*54fd6939SJiyong Park __RO_END__ = .; 51*54fd6939SJiyong Park } >RAM 52*54fd6939SJiyong Park 53*54fd6939SJiyong Park ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 54*54fd6939SJiyong Park "cpu_ops not defined for this platform.") 55*54fd6939SJiyong Park 56*54fd6939SJiyong Park /* 57*54fd6939SJiyong Park * Define a linker symbol to mark start of the RW memory area for this 58*54fd6939SJiyong Park * image. 59*54fd6939SJiyong Park */ 60*54fd6939SJiyong Park __RW_START__ = . ; 61*54fd6939SJiyong Park 62*54fd6939SJiyong Park DATA_SECTION >RAM 63*54fd6939SJiyong Park 64*54fd6939SJiyong Park#ifdef BL31_PROGBITS_LIMIT 65*54fd6939SJiyong Park ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.") 66*54fd6939SJiyong Park#endif 67*54fd6939SJiyong Park 68*54fd6939SJiyong Park STACK_SECTION >RAM 69*54fd6939SJiyong Park BSS_SECTION >RAM 70*54fd6939SJiyong Park __RW_END__ = __BSS_END__; 71*54fd6939SJiyong Park 72*54fd6939SJiyong Park ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.") 73*54fd6939SJiyong Park 74*54fd6939SJiyong Park XLAT_TABLE_SECTION >RAM2 75*54fd6939SJiyong Park 76*54fd6939SJiyong Park#if USE_COHERENT_MEM 77*54fd6939SJiyong Park /* 78*54fd6939SJiyong Park * The base address of the coherent memory section must be page-aligned (4K) 79*54fd6939SJiyong Park * to guarantee that the coherent data are stored on their own pages and 80*54fd6939SJiyong Park * are not mixed with normal data. This is required to set up the correct 81*54fd6939SJiyong Park * memory attributes for the coherent data page tables. 82*54fd6939SJiyong Park */ 83*54fd6939SJiyong Park coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { 84*54fd6939SJiyong Park __COHERENT_RAM_START__ = .; 85*54fd6939SJiyong Park /* 86*54fd6939SJiyong Park * Bakery locks are stored in coherent memory 87*54fd6939SJiyong Park * 88*54fd6939SJiyong Park * Each lock's data is contiguous and fully allocated by the compiler 89*54fd6939SJiyong Park */ 90*54fd6939SJiyong Park *(bakery_lock) 91*54fd6939SJiyong Park *(tzfw_coherent_mem) 92*54fd6939SJiyong Park __COHERENT_RAM_END_UNALIGNED__ = .; 93*54fd6939SJiyong Park /* 94*54fd6939SJiyong Park * Memory page(s) mapped to this section will be marked 95*54fd6939SJiyong Park * as device memory. No other unexpected data must creep in. 96*54fd6939SJiyong Park * Ensure the rest of the current memory page is unused. 97*54fd6939SJiyong Park */ 98*54fd6939SJiyong Park . = ALIGN(PAGE_SIZE); 99*54fd6939SJiyong Park __COHERENT_RAM_END__ = .; 100*54fd6939SJiyong Park } >RAM2 101*54fd6939SJiyong Park#endif 102*54fd6939SJiyong Park 103*54fd6939SJiyong Park /* 104*54fd6939SJiyong Park * Define a linker symbol to mark end of the RW memory area for this 105*54fd6939SJiyong Park * image. 106*54fd6939SJiyong Park */ 107*54fd6939SJiyong Park __BL31_END__ = .; 108*54fd6939SJiyong Park 109*54fd6939SJiyong Park __BSS_SIZE__ = SIZEOF(.bss); 110*54fd6939SJiyong Park#if USE_COHERENT_MEM 111*54fd6939SJiyong Park __COHERENT_RAM_UNALIGNED_SIZE__ = 112*54fd6939SJiyong Park __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 113*54fd6939SJiyong Park#endif 114*54fd6939SJiyong Park 115*54fd6939SJiyong Park ASSERT(. <= TZRAM2_LIMIT, "TZRAM2 image has exceeded its limit.") 116*54fd6939SJiyong Park} 117