1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #include <stdbool.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park #include <arch.h> 10*54fd6939SJiyong Park #include <arch_helpers.h> 11*54fd6939SJiyong Park #include <common/debug.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #include <plat_imx8.h> 14*54fd6939SJiyong Park #include <sci/sci.h> 15*54fd6939SJiyong Park imx_system_off(void)16*54fd6939SJiyong Parkvoid __dead2 imx_system_off(void) 17*54fd6939SJiyong Park { 18*54fd6939SJiyong Park sc_pm_set_sys_power_mode(ipc_handle, SC_PM_PW_MODE_OFF); 19*54fd6939SJiyong Park wfi(); 20*54fd6939SJiyong Park ERROR("power off failed.\n"); 21*54fd6939SJiyong Park panic(); 22*54fd6939SJiyong Park } 23*54fd6939SJiyong Park imx_system_reset(void)24*54fd6939SJiyong Parkvoid __dead2 imx_system_reset(void) 25*54fd6939SJiyong Park { 26*54fd6939SJiyong Park sc_pm_reset(ipc_handle, SC_PM_RESET_TYPE_BOARD); 27*54fd6939SJiyong Park wfi(); 28*54fd6939SJiyong Park ERROR("system reset failed.\n"); 29*54fd6939SJiyong Park panic(); 30*54fd6939SJiyong Park } 31*54fd6939SJiyong Park imx_validate_power_state(unsigned int power_state,psci_power_state_t * req_state)32*54fd6939SJiyong Parkint imx_validate_power_state(unsigned int power_state, 33*54fd6939SJiyong Park psci_power_state_t *req_state) 34*54fd6939SJiyong Park { 35*54fd6939SJiyong Park int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 36*54fd6939SJiyong Park int pwr_type = psci_get_pstate_type(power_state); 37*54fd6939SJiyong Park int state_id = psci_get_pstate_id(power_state); 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park if (pwr_lvl > PLAT_MAX_PWR_LVL) 40*54fd6939SJiyong Park return PSCI_E_INVALID_PARAMS; 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park if (pwr_type == PSTATE_TYPE_POWERDOWN) { 43*54fd6939SJiyong Park req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; 44*54fd6939SJiyong Park if (!state_id) 45*54fd6939SJiyong Park req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_RET_STATE; 46*54fd6939SJiyong Park else 47*54fd6939SJiyong Park req_state->pwr_domain_state[MPIDR_AFFLVL1] = PLAT_MAX_OFF_STATE; 48*54fd6939SJiyong Park } 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park return PSCI_E_SUCCESS; 51*54fd6939SJiyong Park } 52*54fd6939SJiyong Park imx_get_sys_suspend_power_state(psci_power_state_t * req_state)53*54fd6939SJiyong Parkvoid imx_get_sys_suspend_power_state(psci_power_state_t *req_state) 54*54fd6939SJiyong Park { 55*54fd6939SJiyong Park unsigned int i; 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park /* CPU & cluster off, system in retention */ 58*54fd6939SJiyong Park for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) 59*54fd6939SJiyong Park req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; 60*54fd6939SJiyong Park req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; 61*54fd6939SJiyong Park } 62*54fd6939SJiyong Park 63