1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef HI3798CV200_H 8*54fd6939SJiyong Park #define HI3798CV200_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <lib/utils_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* PL011 */ 13*54fd6939SJiyong Park #define PL011_UART0_BASE (0xF8B00000) 14*54fd6939SJiyong Park #define PL011_BAUDRATE (115200) 15*54fd6939SJiyong Park #define PL011_UART0_CLK_IN_HZ (75000000) 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park /* Sys Counter */ 18*54fd6939SJiyong Park #define SYS_COUNTER_FREQ_IN_TICKS (24000000) 19*54fd6939SJiyong Park #define SYS_COUNTER_FREQ_IN_MHZ (24) 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park /* Timer */ 22*54fd6939SJiyong Park #define SEC_TIMER0_BASE (0xF8008000) 23*54fd6939SJiyong Park #define TIMER00_LOAD (SEC_TIMER0_BASE + 0x000) 24*54fd6939SJiyong Park #define TIMER00_VALUE (SEC_TIMER0_BASE + 0x004) 25*54fd6939SJiyong Park #define TIMER00_CONTROL (SEC_TIMER0_BASE + 0x008) 26*54fd6939SJiyong Park #define TIMER00_BGLOAD (SEC_TIMER0_BASE + 0x018) 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park #define SEC_TIMER2_BASE (0xF8009000) 29*54fd6939SJiyong Park #define TIMER20_LOAD (SEC_TIMER2_BASE + 0x000) 30*54fd6939SJiyong Park #define TIMER20_VALUE (SEC_TIMER2_BASE + 0x004) 31*54fd6939SJiyong Park #define TIMER20_CONTROL (SEC_TIMER2_BASE + 0x008) 32*54fd6939SJiyong Park #define TIMER20_BGLOAD (SEC_TIMER2_BASE + 0x018) 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park /* GPIO */ 35*54fd6939SJiyong Park #define GPIO_MAX (13) 36*54fd6939SJiyong Park #define GPIO_BASE(x) (x != 5 ? \ 37*54fd6939SJiyong Park 0xf820000 + x * 0x1000 : 0xf8004000) 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park /* SCTL */ 40*54fd6939SJiyong Park #define REG_BASE_SCTL (0xF8000000) 41*54fd6939SJiyong Park #define REG_SC_GEN12 (0x00B0) 42*54fd6939SJiyong Park 43*54fd6939SJiyong Park /* CRG */ 44*54fd6939SJiyong Park #define REG_BASE_CRG (0xF8A22000) 45*54fd6939SJiyong Park #define REG_CPU_LP (0x48) 46*54fd6939SJiyong Park #define REG_CPU_RST (0x50) 47*54fd6939SJiyong Park #define REG_PERI_CRG39 (0x9C) 48*54fd6939SJiyong Park #define REG_PERI_CRG40 (0xA0) 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park /* MCI */ 51*54fd6939SJiyong Park #define REG_BASE_MCI (0xF9830000) 52*54fd6939SJiyong Park #define MCI_CDETECT (0x50) 53*54fd6939SJiyong Park #define MCI_VERID (0x6C) 54*54fd6939SJiyong Park #define MCI_VERID_VALUE (0x5342250A) 55*54fd6939SJiyong Park #define MCI_VERID_VALUE2 (0x5342270A) 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park /* EMMC */ 58*54fd6939SJiyong Park #define REG_EMMC_PERI_CRG REG_PERI_CRG40 59*54fd6939SJiyong Park #define REG_SDCARD_PERI_CRG REG_PERI_CRG39 60*54fd6939SJiyong Park #define EMMC_CLK_MASK (0x7 << 8) 61*54fd6939SJiyong Park #define EMMC_SRST_REQ (0x1 << 4) 62*54fd6939SJiyong Park #define EMMC_CKEN (0x1 << 1) 63*54fd6939SJiyong Park #define EMMC_BUS_CKEN (0x1 << 0) 64*54fd6939SJiyong Park #define EMMC_CLK_100M (0 << 8) 65*54fd6939SJiyong Park #define EMMC_CLK_50M (1 << 8) 66*54fd6939SJiyong Park #define EMMC_CLK_25M (2 << 8) 67*54fd6939SJiyong Park 68*54fd6939SJiyong Park #define EMMC_DESC_SIZE U(0x00100000) /* 1MB */ 69*54fd6939SJiyong Park #define EMMC_INIT_PARAMS(base) \ 70*54fd6939SJiyong Park { .bus_width = MMC_BUS_WIDTH_8, \ 71*54fd6939SJiyong Park .clk_rate = 25 * 1000 * 1000, \ 72*54fd6939SJiyong Park .desc_base = (base), \ 73*54fd6939SJiyong Park .desc_size = EMMC_DESC_SIZE, \ 74*54fd6939SJiyong Park .flags = MMC_FLAG_CMD23, \ 75*54fd6939SJiyong Park .reg_base = REG_BASE_MCI, \ 76*54fd6939SJiyong Park } 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park /* GIC-400 */ 79*54fd6939SJiyong Park #define GICD_BASE (0xF1001000) 80*54fd6939SJiyong Park #define GICC_BASE (0xF1002000) 81*54fd6939SJiyong Park #define GICR_BASE (0xF1000000) 82*54fd6939SJiyong Park 83*54fd6939SJiyong Park /* FIQ platform related define */ 84*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_0 8 85*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_1 9 86*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_2 10 87*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_3 11 88*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_4 12 89*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_5 13 90*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_6 14 91*54fd6939SJiyong Park #define HISI_IRQ_SEC_SGI_7 15 92*54fd6939SJiyong Park #define HISI_IRQ_SEC_PPI_0 29 93*54fd6939SJiyong Park #define HISI_IRQ_SEC_TIMER0 60 94*54fd6939SJiyong Park #define HISI_IRQ_SEC_TIMER1 50 95*54fd6939SJiyong Park #define HISI_IRQ_SEC_TIMER2 52 96*54fd6939SJiyong Park #define HISI_IRQ_SEC_TIMER3 88 97*54fd6939SJiyong Park #define HISI_IRQ_SEC_AXI 110 98*54fd6939SJiyong Park 99*54fd6939SJiyong Park /* Watchdog */ 100*54fd6939SJiyong Park #define HISI_WDG0_BASE (0xF8A2C000) 101*54fd6939SJiyong Park 102*54fd6939SJiyong Park #define HISI_TZPC_BASE (0xF8A80000) 103*54fd6939SJiyong Park #define HISI_TZPC_SEC_ATTR_CTRL (HISI_TZPC_BASE + 0x10) 104*54fd6939SJiyong Park 105*54fd6939SJiyong Park #endif /* HI3798CV200_H */ 106