1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef HIKEY960_DEF_H 8*54fd6939SJiyong Park #define HIKEY960_DEF_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <common/tbbr/tbbr_img_def.h> 11*54fd6939SJiyong Park #include <plat/common/common_def.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #define DDR_BASE 0x0 14*54fd6939SJiyong Park #define DDR_SIZE 0xE0000000 15*54fd6939SJiyong Park 16*54fd6939SJiyong Park #define DEVICE_BASE 0xE0000000 17*54fd6939SJiyong Park #define DEVICE_SIZE 0x20000000 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park /* Memory location options for TSP */ 20*54fd6939SJiyong Park #define HIKEY960_SRAM_ID 0 21*54fd6939SJiyong Park #define HIKEY960_DRAM_ID 1 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park /* 24*54fd6939SJiyong Park * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several 25*54fd6939SJiyong Park * regions: 26*54fd6939SJiyong Park * - Secure DDR (default is the top 16MB) used by OP-TEE 27*54fd6939SJiyong Park * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 28*54fd6939SJiyong Park * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 29*54fd6939SJiyong Park * - Non-secure DDR (8MB) reserved for OP-TEE's future use 30*54fd6939SJiyong Park */ 31*54fd6939SJiyong Park #define DDR_SEC_SIZE 0x01000000 32*54fd6939SJiyong Park #define DDR_SEC_BASE 0x3F000000 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park #define DDR_SDP_SIZE 0x00400000 35*54fd6939SJiyong Park #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ 36*54fd6939SJiyong Park DDR_SDP_SIZE) 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park /* 39*54fd6939SJiyong Park * PL011 related constants 40*54fd6939SJiyong Park */ 41*54fd6939SJiyong Park #define PL011_UART5_BASE 0xFDF05000 42*54fd6939SJiyong Park #define PL011_UART6_BASE 0xFFF32000 43*54fd6939SJiyong Park #define PL011_BAUDRATE 115200 44*54fd6939SJiyong Park #define PL011_UART_CLK_IN_HZ 19200000 45*54fd6939SJiyong Park 46*54fd6939SJiyong Park #define UFS_BASE 0 47*54fd6939SJiyong Park 48*54fd6939SJiyong Park #define HIKEY960_UFS_DESC_BASE 0x20000000 49*54fd6939SJiyong Park #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ 50*54fd6939SJiyong Park #define HIKEY960_UFS_DATA_BASE 0x10000000 51*54fd6939SJiyong Park #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ 52*54fd6939SJiyong Park 53*54fd6939SJiyong Park #endif /* HIKEY960_DEF_H */ 54