1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef HI6220_H 8*54fd6939SJiyong Park #define HI6220_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <hi6220_regs_acpu.h> 11*54fd6939SJiyong Park #include <hi6220_regs_ao.h> 12*54fd6939SJiyong Park #include <hi6220_regs_peri.h> 13*54fd6939SJiyong Park #include <hi6220_regs_pin.h> 14*54fd6939SJiyong Park #include <hi6220_regs_pmctrl.h> 15*54fd6939SJiyong Park 16*54fd6939SJiyong Park /******************************************************************************* 17*54fd6939SJiyong Park * Implementation defined ACTLR_EL2 bit definitions 18*54fd6939SJiyong Park ******************************************************************************/ 19*54fd6939SJiyong Park #define ACTLR_EL2_L2ACTLR_BIT (1 << 6) 20*54fd6939SJiyong Park #define ACTLR_EL2_L2ECTLR_BIT (1 << 5) 21*54fd6939SJiyong Park #define ACTLR_EL2_L2CTLR_BIT (1 << 4) 22*54fd6939SJiyong Park #define ACTLR_EL2_CPUECTLR_BIT (1 << 1) 23*54fd6939SJiyong Park #define ACTLR_EL2_CPUACTLR_BIT (1 << 0) 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park /******************************************************************************* 26*54fd6939SJiyong Park * Implementation defined ACTLR_EL3 bit definitions 27*54fd6939SJiyong Park ******************************************************************************/ 28*54fd6939SJiyong Park #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) 29*54fd6939SJiyong Park #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) 30*54fd6939SJiyong Park #define ACTLR_EL3_L2CTLR_BIT (1 << 4) 31*54fd6939SJiyong Park #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) 32*54fd6939SJiyong Park #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park /******************************************************************************* 35*54fd6939SJiyong Park * CCI-400 related constants 36*54fd6939SJiyong Park ******************************************************************************/ 37*54fd6939SJiyong Park #define CCI400_BASE 0xF6E90000 38*54fd6939SJiyong Park #define CCI400_SL_IFACE3_CLUSTER_IX 3 39*54fd6939SJiyong Park #define CCI400_SL_IFACE4_CLUSTER_IX 4 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park #define DWMMC0_BASE 0xF723D000 42*54fd6939SJiyong Park 43*54fd6939SJiyong Park #define DWUSB_BASE 0xF72C0000 44*54fd6939SJiyong Park 45*54fd6939SJiyong Park #define EDMAC_BASE 0xf7370000 46*54fd6939SJiyong Park #define EDMAC_SEC_CTRL (EDMAC_BASE + 0x694) 47*54fd6939SJiyong Park #define EDMAC_AXI_CONF(x) (EDMAC_BASE + 0x820 + (x << 6)) 48*54fd6939SJiyong Park #define EDMAC_SEC_CTRL_INTR_SEC (1 << 1) 49*54fd6939SJiyong Park #define EDMAC_SEC_CTRL_GLOBAL_SEC (1 << 0) 50*54fd6939SJiyong Park #define EDMAC_CHANNEL_NUMS 16 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park #define PMUSSI_BASE 0xF8000000 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park #define SP804_TIMER0_BASE 0xF8008000 55*54fd6939SJiyong Park 56*54fd6939SJiyong Park #define GPIO0_BASE 0xF8011000 57*54fd6939SJiyong Park #define GPIO1_BASE 0xF8012000 58*54fd6939SJiyong Park #define GPIO2_BASE 0xF8013000 59*54fd6939SJiyong Park #define GPIO3_BASE 0xF8014000 60*54fd6939SJiyong Park #define GPIO4_BASE 0xF7020000 61*54fd6939SJiyong Park #define GPIO5_BASE 0xF7021000 62*54fd6939SJiyong Park #define GPIO6_BASE 0xF7022000 63*54fd6939SJiyong Park #define GPIO7_BASE 0xF7023000 64*54fd6939SJiyong Park #define GPIO8_BASE 0xF7024000 65*54fd6939SJiyong Park #define GPIO9_BASE 0xF7025000 66*54fd6939SJiyong Park #define GPIO10_BASE 0xF7026000 67*54fd6939SJiyong Park #define GPIO11_BASE 0xF7027000 68*54fd6939SJiyong Park #define GPIO12_BASE 0xF7028000 69*54fd6939SJiyong Park #define GPIO13_BASE 0xF7029000 70*54fd6939SJiyong Park #define GPIO14_BASE 0xF702A000 71*54fd6939SJiyong Park #define GPIO15_BASE 0xF702B000 72*54fd6939SJiyong Park #define GPIO16_BASE 0xF702C000 73*54fd6939SJiyong Park #define GPIO17_BASE 0xF702D000 74*54fd6939SJiyong Park #define GPIO18_BASE 0xF702E000 75*54fd6939SJiyong Park #define GPIO19_BASE 0xF702F000 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park #endif /* HI6220_H */ 78