1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <assert.h>
8*54fd6939SJiyong Park #include <bl31/interrupt_mgmt.h>
9*54fd6939SJiyong Park #include <common/bl_common.h>
10*54fd6939SJiyong Park #include <common/ep_info.h>
11*54fd6939SJiyong Park #include <lib/mmio.h>
12*54fd6939SJiyong Park #include <lib/xlat_tables/xlat_tables_v2.h>
13*54fd6939SJiyong Park #include <platform_def.h>
14*54fd6939SJiyong Park #include <stdint.h>
15*54fd6939SJiyong Park
16*54fd6939SJiyong Park /*******************************************************************************
17*54fd6939SJiyong Park * Platform memory map regions
18*54fd6939SJiyong Park ******************************************************************************/
19*54fd6939SJiyong Park #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
20*54fd6939SJiyong Park AML_NSDRAM0_SIZE, \
21*54fd6939SJiyong Park MT_MEMORY | MT_RW | MT_NS)
22*54fd6939SJiyong Park
23*54fd6939SJiyong Park #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
24*54fd6939SJiyong Park AML_NSDRAM1_SIZE, \
25*54fd6939SJiyong Park MT_MEMORY | MT_RW | MT_NS)
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
28*54fd6939SJiyong Park AML_SEC_DEVICE0_SIZE, \
29*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
30*54fd6939SJiyong Park
31*54fd6939SJiyong Park #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
32*54fd6939SJiyong Park AML_SEC_DEVICE1_SIZE, \
33*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
34*54fd6939SJiyong Park
35*54fd6939SJiyong Park #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
36*54fd6939SJiyong Park AML_TZRAM_SIZE, \
37*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
38*54fd6939SJiyong Park
39*54fd6939SJiyong Park #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
40*54fd6939SJiyong Park AML_SEC_DEVICE2_SIZE, \
41*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
42*54fd6939SJiyong Park
43*54fd6939SJiyong Park #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
44*54fd6939SJiyong Park AML_SEC_DEVICE3_SIZE, \
45*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
46*54fd6939SJiyong Park
47*54fd6939SJiyong Park static const mmap_region_t gxl_mmap[] = {
48*54fd6939SJiyong Park MAP_NSDRAM0,
49*54fd6939SJiyong Park MAP_NSDRAM1,
50*54fd6939SJiyong Park MAP_SEC_DEVICE0,
51*54fd6939SJiyong Park MAP_SEC_DEVICE1,
52*54fd6939SJiyong Park MAP_TZRAM,
53*54fd6939SJiyong Park MAP_SEC_DEVICE2,
54*54fd6939SJiyong Park MAP_SEC_DEVICE3,
55*54fd6939SJiyong Park {0}
56*54fd6939SJiyong Park };
57*54fd6939SJiyong Park
58*54fd6939SJiyong Park /*******************************************************************************
59*54fd6939SJiyong Park * Per-image regions
60*54fd6939SJiyong Park ******************************************************************************/
61*54fd6939SJiyong Park #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
62*54fd6939SJiyong Park BL31_END - BL31_BASE, \
63*54fd6939SJiyong Park MT_MEMORY | MT_RW | MT_SECURE)
64*54fd6939SJiyong Park
65*54fd6939SJiyong Park #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
66*54fd6939SJiyong Park BL_CODE_END - BL_CODE_BASE, \
67*54fd6939SJiyong Park MT_CODE | MT_SECURE)
68*54fd6939SJiyong Park
69*54fd6939SJiyong Park #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
70*54fd6939SJiyong Park BL_RO_DATA_END - BL_RO_DATA_BASE, \
71*54fd6939SJiyong Park MT_RO_DATA | MT_SECURE)
72*54fd6939SJiyong Park
73*54fd6939SJiyong Park #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
74*54fd6939SJiyong Park BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
75*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
76*54fd6939SJiyong Park
77*54fd6939SJiyong Park /*******************************************************************************
78*54fd6939SJiyong Park * Function that sets up the translation tables.
79*54fd6939SJiyong Park ******************************************************************************/
aml_setup_page_tables(void)80*54fd6939SJiyong Park void aml_setup_page_tables(void)
81*54fd6939SJiyong Park {
82*54fd6939SJiyong Park #if IMAGE_BL31
83*54fd6939SJiyong Park const mmap_region_t gxl_bl_mmap[] = {
84*54fd6939SJiyong Park MAP_BL31,
85*54fd6939SJiyong Park MAP_BL_CODE,
86*54fd6939SJiyong Park MAP_BL_RO_DATA,
87*54fd6939SJiyong Park #if USE_COHERENT_MEM
88*54fd6939SJiyong Park MAP_BL_COHERENT,
89*54fd6939SJiyong Park #endif
90*54fd6939SJiyong Park {0}
91*54fd6939SJiyong Park };
92*54fd6939SJiyong Park #endif
93*54fd6939SJiyong Park
94*54fd6939SJiyong Park mmap_add(gxl_bl_mmap);
95*54fd6939SJiyong Park
96*54fd6939SJiyong Park mmap_add(gxl_mmap);
97*54fd6939SJiyong Park
98*54fd6939SJiyong Park init_xlat_tables();
99*54fd6939SJiyong Park }
100*54fd6939SJiyong Park
101*54fd6939SJiyong Park /*******************************************************************************
102*54fd6939SJiyong Park * Function that returns the system counter frequency
103*54fd6939SJiyong Park ******************************************************************************/
plat_get_syscnt_freq2(void)104*54fd6939SJiyong Park unsigned int plat_get_syscnt_freq2(void)
105*54fd6939SJiyong Park {
106*54fd6939SJiyong Park uint32_t val;
107*54fd6939SJiyong Park
108*54fd6939SJiyong Park val = mmio_read_32(AML_SYS_CPU_CFG7);
109*54fd6939SJiyong Park val &= 0xFDFFFFFF;
110*54fd6939SJiyong Park mmio_write_32(AML_SYS_CPU_CFG7, val);
111*54fd6939SJiyong Park
112*54fd6939SJiyong Park val = mmio_read_32(AML_AO_TIMESTAMP_CNTL);
113*54fd6939SJiyong Park val &= 0xFFFFFE00;
114*54fd6939SJiyong Park mmio_write_32(AML_AO_TIMESTAMP_CNTL, val);
115*54fd6939SJiyong Park
116*54fd6939SJiyong Park return AML_OSC24M_CLK_IN_HZ;
117*54fd6939SJiyong Park }
118