1*54fd6939SJiyong Park# 2*54fd6939SJiyong Park# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park# 4*54fd6939SJiyong Park# SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park# 6*54fd6939SJiyong Park 7*54fd6939SJiyong Parkinclude lib/xlat_tables_v2/xlat_tables.mk 8*54fd6939SJiyong Park 9*54fd6939SJiyong ParkAML_PLAT := plat/amlogic 10*54fd6939SJiyong ParkAML_PLAT_SOC := ${AML_PLAT}/${PLAT} 11*54fd6939SJiyong ParkAML_PLAT_COMMON := ${AML_PLAT}/common 12*54fd6939SJiyong Park 13*54fd6939SJiyong ParkPLAT_INCLUDES := -Iinclude/drivers/amlogic/ \ 14*54fd6939SJiyong Park -I${AML_PLAT_SOC}/include \ 15*54fd6939SJiyong Park -I${AML_PLAT_COMMON}/include 16*54fd6939SJiyong Park 17*54fd6939SJiyong ParkGIC_SOURCES := drivers/arm/gic/common/gic_common.c \ 18*54fd6939SJiyong Park drivers/arm/gic/v2/gicv2_main.c \ 19*54fd6939SJiyong Park drivers/arm/gic/v2/gicv2_helpers.c \ 20*54fd6939SJiyong Park plat/common/plat_gicv2.c 21*54fd6939SJiyong Park 22*54fd6939SJiyong ParkBL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ 23*54fd6939SJiyong Park plat/common/plat_psci_common.c \ 24*54fd6939SJiyong Park drivers/amlogic/console/aarch64/meson_console.S \ 25*54fd6939SJiyong Park ${AML_PLAT_SOC}/${PLAT}_bl31_setup.c \ 26*54fd6939SJiyong Park ${AML_PLAT_SOC}/${PLAT}_pm.c \ 27*54fd6939SJiyong Park ${AML_PLAT_SOC}/${PLAT}_common.c \ 28*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aarch64/aml_helpers.S \ 29*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aml_efuse.c \ 30*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aml_mhu.c \ 31*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aml_scpi.c \ 32*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aml_sip_svc.c \ 33*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aml_thermal.c \ 34*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aml_topology.c \ 35*54fd6939SJiyong Park ${AML_PLAT_COMMON}/aml_console.c \ 36*54fd6939SJiyong Park ${XLAT_TABLES_LIB_SRCS} \ 37*54fd6939SJiyong Park ${GIC_SOURCES} 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park# Tune compiler for Cortex-A53 40*54fd6939SJiyong Parkifeq ($(notdir $(CC)),armclang) 41*54fd6939SJiyong Park TF_CFLAGS_aarch64 += -mcpu=cortex-a53 42*54fd6939SJiyong Parkelse ifneq ($(findstring clang,$(notdir $(CC))),) 43*54fd6939SJiyong Park TF_CFLAGS_aarch64 += -mcpu=cortex-a53 44*54fd6939SJiyong Parkelse 45*54fd6939SJiyong Park TF_CFLAGS_aarch64 += -mtune=cortex-a53 46*54fd6939SJiyong Parkendif 47*54fd6939SJiyong Park 48*54fd6939SJiyong Park# Build config flags 49*54fd6939SJiyong Park# ------------------ 50*54fd6939SJiyong Park 51*54fd6939SJiyong Park# Enable all errata workarounds for Cortex-A53 52*54fd6939SJiyong ParkERRATA_A53_826319 := 1 53*54fd6939SJiyong ParkERRATA_A53_835769 := 1 54*54fd6939SJiyong ParkERRATA_A53_836870 := 1 55*54fd6939SJiyong ParkERRATA_A53_843419 := 1 56*54fd6939SJiyong ParkERRATA_A53_855873 := 1 57*54fd6939SJiyong Park 58*54fd6939SJiyong ParkWORKAROUND_CVE_2017_5715 := 0 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park# Have different sections for code and rodata 61*54fd6939SJiyong ParkSEPARATE_CODE_AND_RODATA := 1 62*54fd6939SJiyong Park 63*54fd6939SJiyong Park# Use Coherent memory 64*54fd6939SJiyong ParkUSE_COHERENT_MEM := 1 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park# Verify build config 67*54fd6939SJiyong Park# ------------------- 68*54fd6939SJiyong Park 69*54fd6939SJiyong Parkifneq (${RESET_TO_BL31}, 0) 70*54fd6939SJiyong Park $(error Error: ${PLAT} needs RESET_TO_BL31=0) 71*54fd6939SJiyong Parkendif 72*54fd6939SJiyong Park 73*54fd6939SJiyong Parkifeq (${ARCH},aarch32) 74*54fd6939SJiyong Park $(error Error: AArch32 not supported on ${PLAT}) 75*54fd6939SJiyong Parkendif 76