1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef GXBB_DEF_H 8*54fd6939SJiyong Park #define GXBB_DEF_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <lib/utils_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /******************************************************************************* 13*54fd6939SJiyong Park * System oscillator 14*54fd6939SJiyong Park ******************************************************************************/ 15*54fd6939SJiyong Park #define AML_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */ 16*54fd6939SJiyong Park 17*54fd6939SJiyong Park /******************************************************************************* 18*54fd6939SJiyong Park * Memory regions 19*54fd6939SJiyong Park ******************************************************************************/ 20*54fd6939SJiyong Park #define AML_NSDRAM0_BASE UL(0x01000000) 21*54fd6939SJiyong Park #define AML_NSDRAM0_SIZE UL(0x0F000000) 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park #define AML_NSDRAM1_BASE UL(0x10000000) 24*54fd6939SJiyong Park #define AML_NSDRAM1_SIZE UL(0x00100000) 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park #define BL31_BASE UL(0x10100000) 27*54fd6939SJiyong Park #define BL31_SIZE UL(0x000C0000) 28*54fd6939SJiyong Park #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 29*54fd6939SJiyong Park 30*54fd6939SJiyong Park /* Shared memory used for SMC services */ 31*54fd6939SJiyong Park #define AML_SHARE_MEM_INPUT_BASE UL(0x100FE000) 32*54fd6939SJiyong Park #define AML_SHARE_MEM_OUTPUT_BASE UL(0x100FF000) 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park #define AML_SEC_DEVICE0_BASE UL(0xC0000000) 35*54fd6939SJiyong Park #define AML_SEC_DEVICE0_SIZE UL(0x09000000) 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park #define AML_SEC_DEVICE1_BASE UL(0xD0040000) 38*54fd6939SJiyong Park #define AML_SEC_DEVICE1_SIZE UL(0x00008000) 39*54fd6939SJiyong Park 40*54fd6939SJiyong Park #define AML_TZRAM_BASE UL(0xD9000000) 41*54fd6939SJiyong Park #define AML_TZRAM_SIZE UL(0x00014000) 42*54fd6939SJiyong Park /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */ 43*54fd6939SJiyong Park 44*54fd6939SJiyong Park /* Mailboxes */ 45*54fd6939SJiyong Park #define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800) 46*54fd6939SJiyong Park #define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00) 47*54fd6939SJiyong Park #define AML_PSCI_MAILBOX_BASE UL(0xD9013F00) 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park #define AML_TZROM_BASE UL(0xD9040000) 50*54fd6939SJiyong Park #define AML_TZROM_SIZE UL(0x00010000) 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park #define AML_SEC_DEVICE2_BASE UL(0xDA000000) 53*54fd6939SJiyong Park #define AML_SEC_DEVICE2_SIZE UL(0x00200000) 54*54fd6939SJiyong Park 55*54fd6939SJiyong Park #define AML_SEC_DEVICE3_BASE UL(0xDA800000) 56*54fd6939SJiyong Park #define AML_SEC_DEVICE3_SIZE UL(0x00200000) 57*54fd6939SJiyong Park 58*54fd6939SJiyong Park /******************************************************************************* 59*54fd6939SJiyong Park * GIC-400 and interrupt handling related constants 60*54fd6939SJiyong Park ******************************************************************************/ 61*54fd6939SJiyong Park #define AML_GICD_BASE UL(0xC4301000) 62*54fd6939SJiyong Park #define AML_GICC_BASE UL(0xC4302000) 63*54fd6939SJiyong Park 64*54fd6939SJiyong Park #define IRQ_SEC_PHY_TIMER 29 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park #define IRQ_SEC_SGI_0 8 67*54fd6939SJiyong Park #define IRQ_SEC_SGI_1 9 68*54fd6939SJiyong Park #define IRQ_SEC_SGI_2 10 69*54fd6939SJiyong Park #define IRQ_SEC_SGI_3 11 70*54fd6939SJiyong Park #define IRQ_SEC_SGI_4 12 71*54fd6939SJiyong Park #define IRQ_SEC_SGI_5 13 72*54fd6939SJiyong Park #define IRQ_SEC_SGI_6 14 73*54fd6939SJiyong Park #define IRQ_SEC_SGI_7 15 74*54fd6939SJiyong Park 75*54fd6939SJiyong Park /******************************************************************************* 76*54fd6939SJiyong Park * UART definitions 77*54fd6939SJiyong Park ******************************************************************************/ 78*54fd6939SJiyong Park #define AML_UART0_AO_BASE UL(0xC81004C0) 79*54fd6939SJiyong Park #define AML_UART0_AO_CLK_IN_HZ AML_OSC24M_CLK_IN_HZ 80*54fd6939SJiyong Park #define AML_UART_BAUDRATE U(115200) 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park /******************************************************************************* 83*54fd6939SJiyong Park * Memory-mapped I/O Registers 84*54fd6939SJiyong Park ******************************************************************************/ 85*54fd6939SJiyong Park #define AML_AO_TIMESTAMP_CNTL UL(0xC81000B4) 86*54fd6939SJiyong Park 87*54fd6939SJiyong Park #define AML_SYS_CPU_CFG7 UL(0xC8834664) 88*54fd6939SJiyong Park 89*54fd6939SJiyong Park #define AML_AO_RTI_STATUS_REG3 UL(0xDA10001C) 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park #define AML_HIU_MAILBOX_SET_0 UL(0xDA83C404) 92*54fd6939SJiyong Park #define AML_HIU_MAILBOX_STAT_0 UL(0xDA83C408) 93*54fd6939SJiyong Park #define AML_HIU_MAILBOX_CLR_0 UL(0xDA83C40C) 94*54fd6939SJiyong Park #define AML_HIU_MAILBOX_SET_3 UL(0xDA83C428) 95*54fd6939SJiyong Park #define AML_HIU_MAILBOX_STAT_3 UL(0xDA83C42C) 96*54fd6939SJiyong Park #define AML_HIU_MAILBOX_CLR_3 UL(0xDA83C430) 97*54fd6939SJiyong Park 98*54fd6939SJiyong Park #define AML_SHA_DMA_BASE UL(0xC883E000) 99*54fd6939SJiyong Park #define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08) 100*54fd6939SJiyong Park #define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18) 101*54fd6939SJiyong Park 102*54fd6939SJiyong Park /******************************************************************************* 103*54fd6939SJiyong Park * System Monitor Call IDs and arguments 104*54fd6939SJiyong Park ******************************************************************************/ 105*54fd6939SJiyong Park #define AML_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020) 106*54fd6939SJiyong Park #define AML_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021) 107*54fd6939SJiyong Park 108*54fd6939SJiyong Park #define AML_SM_EFUSE_READ U(0x82000030) 109*54fd6939SJiyong Park #define AML_SM_EFUSE_USER_MAX U(0x82000033) 110*54fd6939SJiyong Park 111*54fd6939SJiyong Park #define AML_SM_JTAG_ON U(0x82000040) 112*54fd6939SJiyong Park #define AML_SM_JTAG_OFF U(0x82000041) 113*54fd6939SJiyong Park #define AML_SM_GET_CHIP_ID U(0x82000044) 114*54fd6939SJiyong Park 115*54fd6939SJiyong Park #define AML_JTAG_STATE_ON U(0) 116*54fd6939SJiyong Park #define AML_JTAG_STATE_OFF U(1) 117*54fd6939SJiyong Park 118*54fd6939SJiyong Park #define AML_JTAG_M3_AO U(0) 119*54fd6939SJiyong Park #define AML_JTAG_M3_EE U(1) 120*54fd6939SJiyong Park #define AML_JTAG_A53_AO U(2) 121*54fd6939SJiyong Park #define AML_JTAG_A53_EE U(3) 122*54fd6939SJiyong Park 123*54fd6939SJiyong Park #endif /* GXBB_DEF_H */ 124