1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park
7*54fd6939SJiyong Park #include <assert.h>
8*54fd6939SJiyong Park #include <bl31/interrupt_mgmt.h>
9*54fd6939SJiyong Park #include <common/bl_common.h>
10*54fd6939SJiyong Park #include <common/ep_info.h>
11*54fd6939SJiyong Park #include <lib/mmio.h>
12*54fd6939SJiyong Park #include <lib/xlat_tables/xlat_tables_v2.h>
13*54fd6939SJiyong Park #include <platform_def.h>
14*54fd6939SJiyong Park #include <stdint.h>
15*54fd6939SJiyong Park
16*54fd6939SJiyong Park /*******************************************************************************
17*54fd6939SJiyong Park * Platform memory map regions
18*54fd6939SJiyong Park ******************************************************************************/
19*54fd6939SJiyong Park #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
20*54fd6939SJiyong Park AML_NSDRAM0_SIZE, \
21*54fd6939SJiyong Park MT_MEMORY | MT_RW | MT_NS)
22*54fd6939SJiyong Park
23*54fd6939SJiyong Park #define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \
24*54fd6939SJiyong Park AML_NS_SHARE_MEM_SIZE, \
25*54fd6939SJiyong Park MT_MEMORY | MT_RW | MT_NS)
26*54fd6939SJiyong Park
27*54fd6939SJiyong Park #define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \
28*54fd6939SJiyong Park AML_SEC_SHARE_MEM_SIZE, \
29*54fd6939SJiyong Park MT_MEMORY | MT_RW | MT_SECURE)
30*54fd6939SJiyong Park
31*54fd6939SJiyong Park #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
32*54fd6939SJiyong Park AML_SEC_DEVICE0_SIZE, \
33*54fd6939SJiyong Park MT_DEVICE | MT_RW)
34*54fd6939SJiyong Park
35*54fd6939SJiyong Park #define MAP_HDCP_RX MAP_REGION_FLAT(AML_HDCP_RX_BASE, \
36*54fd6939SJiyong Park AML_HDCP_RX_SIZE, \
37*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
38*54fd6939SJiyong Park
39*54fd6939SJiyong Park #define MAP_HDCP_TX MAP_REGION_FLAT(AML_HDCP_TX_BASE, \
40*54fd6939SJiyong Park AML_HDCP_TX_SIZE, \
41*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
42*54fd6939SJiyong Park
43*54fd6939SJiyong Park #define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \
44*54fd6939SJiyong Park AML_GIC_DEVICE_SIZE, \
45*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
46*54fd6939SJiyong Park
47*54fd6939SJiyong Park #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
48*54fd6939SJiyong Park AML_SEC_DEVICE1_SIZE, \
49*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
50*54fd6939SJiyong Park
51*54fd6939SJiyong Park #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
52*54fd6939SJiyong Park AML_SEC_DEVICE2_SIZE, \
53*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
54*54fd6939SJiyong Park
55*54fd6939SJiyong Park #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
56*54fd6939SJiyong Park AML_TZRAM_SIZE, \
57*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
58*54fd6939SJiyong Park
59*54fd6939SJiyong Park static const mmap_region_t g12a_mmap[] = {
60*54fd6939SJiyong Park MAP_NSDRAM0,
61*54fd6939SJiyong Park MAP_NS_SHARE_MEM,
62*54fd6939SJiyong Park MAP_SEC_SHARE_MEM,
63*54fd6939SJiyong Park MAP_SEC_DEVICE0,
64*54fd6939SJiyong Park MAP_HDCP_RX,
65*54fd6939SJiyong Park MAP_HDCP_TX,
66*54fd6939SJiyong Park MAP_GIC_DEVICE,
67*54fd6939SJiyong Park MAP_SEC_DEVICE1,
68*54fd6939SJiyong Park MAP_SEC_DEVICE2,
69*54fd6939SJiyong Park MAP_TZRAM,
70*54fd6939SJiyong Park {0}
71*54fd6939SJiyong Park };
72*54fd6939SJiyong Park
73*54fd6939SJiyong Park /*******************************************************************************
74*54fd6939SJiyong Park * Per-image regions
75*54fd6939SJiyong Park ******************************************************************************/
76*54fd6939SJiyong Park #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
77*54fd6939SJiyong Park BL31_END - BL31_BASE, \
78*54fd6939SJiyong Park MT_MEMORY | MT_RW | MT_SECURE)
79*54fd6939SJiyong Park
80*54fd6939SJiyong Park #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
81*54fd6939SJiyong Park BL_CODE_END - BL_CODE_BASE, \
82*54fd6939SJiyong Park MT_CODE | MT_SECURE)
83*54fd6939SJiyong Park
84*54fd6939SJiyong Park #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
85*54fd6939SJiyong Park BL_RO_DATA_END - BL_RO_DATA_BASE, \
86*54fd6939SJiyong Park MT_RO_DATA | MT_SECURE)
87*54fd6939SJiyong Park
88*54fd6939SJiyong Park #define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
89*54fd6939SJiyong Park BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
90*54fd6939SJiyong Park MT_DEVICE | MT_RW | MT_SECURE)
91*54fd6939SJiyong Park
92*54fd6939SJiyong Park /*******************************************************************************
93*54fd6939SJiyong Park * Function that sets up the translation tables.
94*54fd6939SJiyong Park ******************************************************************************/
aml_setup_page_tables(void)95*54fd6939SJiyong Park void aml_setup_page_tables(void)
96*54fd6939SJiyong Park {
97*54fd6939SJiyong Park #if IMAGE_BL31
98*54fd6939SJiyong Park const mmap_region_t g12a_bl_mmap[] = {
99*54fd6939SJiyong Park MAP_BL31,
100*54fd6939SJiyong Park MAP_BL_CODE,
101*54fd6939SJiyong Park MAP_BL_RO_DATA,
102*54fd6939SJiyong Park #if USE_COHERENT_MEM
103*54fd6939SJiyong Park MAP_BL_COHERENT,
104*54fd6939SJiyong Park #endif
105*54fd6939SJiyong Park {0}
106*54fd6939SJiyong Park };
107*54fd6939SJiyong Park #endif
108*54fd6939SJiyong Park
109*54fd6939SJiyong Park mmap_add(g12a_bl_mmap);
110*54fd6939SJiyong Park
111*54fd6939SJiyong Park mmap_add(g12a_mmap);
112*54fd6939SJiyong Park
113*54fd6939SJiyong Park init_xlat_tables();
114*54fd6939SJiyong Park }
115*54fd6939SJiyong Park
116*54fd6939SJiyong Park /*******************************************************************************
117*54fd6939SJiyong Park * Function that returns the system counter frequency
118*54fd6939SJiyong Park ******************************************************************************/
plat_get_syscnt_freq2(void)119*54fd6939SJiyong Park unsigned int plat_get_syscnt_freq2(void)
120*54fd6939SJiyong Park {
121*54fd6939SJiyong Park mmio_clrbits_32(AML_SYS_CPU_CFG7, ~0xFDFFFFFF);
122*54fd6939SJiyong Park mmio_clrbits_32(AML_AO_TIMESTAMP_CNTL, ~0xFFFFFE00);
123*54fd6939SJiyong Park
124*54fd6939SJiyong Park return AML_OSC24M_CLK_IN_HZ;
125*54fd6939SJiyong Park }
126