1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #include <platform_def.h> 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park #include <arch.h> 10*54fd6939SJiyong Park #include <plat/common/platform.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park static const unsigned char plat_power_domain_tree_desc[PLAT_MAX_PWR_LVL + 1] = { 13*54fd6939SJiyong Park /* One root node for the SoC */ 14*54fd6939SJiyong Park 1, 15*54fd6939SJiyong Park /* One node for each cluster */ 16*54fd6939SJiyong Park PLATFORM_CLUSTER_COUNT, 17*54fd6939SJiyong Park /* One set of CPUs per cluster */ 18*54fd6939SJiyong Park PLATFORM_MAX_CPUS_PER_CLUSTER, 19*54fd6939SJiyong Park }; 20*54fd6939SJiyong Park plat_core_pos_by_mpidr(u_register_t mpidr)21*54fd6939SJiyong Parkint plat_core_pos_by_mpidr(u_register_t mpidr) 22*54fd6939SJiyong Park { 23*54fd6939SJiyong Park unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); 24*54fd6939SJiyong Park unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park if (MPIDR_AFFLVL3_VAL(mpidr) > 0 || 27*54fd6939SJiyong Park MPIDR_AFFLVL2_VAL(mpidr) > 0 || 28*54fd6939SJiyong Park cluster >= PLATFORM_CLUSTER_COUNT || 29*54fd6939SJiyong Park core >= PLATFORM_MAX_CPUS_PER_CLUSTER) { 30*54fd6939SJiyong Park return -1; 31*54fd6939SJiyong Park } 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park return cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core; 34*54fd6939SJiyong Park } 35*54fd6939SJiyong Park plat_get_power_domain_tree_desc(void)36*54fd6939SJiyong Parkconst unsigned char *plat_get_power_domain_tree_desc(void) 37*54fd6939SJiyong Park { 38*54fd6939SJiyong Park return plat_power_domain_tree_desc; 39*54fd6939SJiyong Park } 40