1*54fd6939SJiyong Park# 2*54fd6939SJiyong Park# Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park# 4*54fd6939SJiyong Park# SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park# 6*54fd6939SJiyong Park 7*54fd6939SJiyong Parkinclude lib/xlat_tables_v2/xlat_tables.mk 8*54fd6939SJiyong Parkinclude lib/libfdt/libfdt.mk 9*54fd6939SJiyong Parkinclude drivers/arm/gic/v2/gicv2.mk 10*54fd6939SJiyong Park 11*54fd6939SJiyong ParkAW_PLAT := plat/allwinner 12*54fd6939SJiyong Park 13*54fd6939SJiyong ParkPLAT_INCLUDES := -Iinclude/plat/arm/common/aarch64 \ 14*54fd6939SJiyong Park -I${AW_PLAT}/common/include \ 15*54fd6939SJiyong Park -I${AW_PLAT}/${PLAT}/include 16*54fd6939SJiyong Park 17*54fd6939SJiyong ParkPLAT_BL_COMMON_SOURCES := drivers/ti/uart/${ARCH}/16550_console.S \ 18*54fd6939SJiyong Park ${XLAT_TABLES_LIB_SRCS} \ 19*54fd6939SJiyong Park ${AW_PLAT}/common/plat_helpers.S \ 20*54fd6939SJiyong Park ${AW_PLAT}/common/sunxi_common.c 21*54fd6939SJiyong Park 22*54fd6939SJiyong ParkBL31_SOURCES += drivers/allwinner/axp/common.c \ 23*54fd6939SJiyong Park ${GICV2_SOURCES} \ 24*54fd6939SJiyong Park drivers/delay_timer/delay_timer.c \ 25*54fd6939SJiyong Park drivers/delay_timer/generic_delay_timer.c \ 26*54fd6939SJiyong Park lib/cpus/${ARCH}/cortex_a53.S \ 27*54fd6939SJiyong Park plat/common/plat_gicv2.c \ 28*54fd6939SJiyong Park plat/common/plat_psci_common.c \ 29*54fd6939SJiyong Park ${AW_PLAT}/common/sunxi_bl31_setup.c \ 30*54fd6939SJiyong Park ${AW_PLAT}/common/sunxi_pm.c \ 31*54fd6939SJiyong Park ${AW_PLAT}/${PLAT}/sunxi_power.c \ 32*54fd6939SJiyong Park ${AW_PLAT}/common/sunxi_security.c \ 33*54fd6939SJiyong Park ${AW_PLAT}/common/sunxi_topology.c 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park# By default, attempt to use SCPI to the ARISC management processor. If SCPI 36*54fd6939SJiyong Park# is not enabled or SCP firmware is not loaded, fall back to a simpler native 37*54fd6939SJiyong Park# implementation that does not support CPU or system suspend. 38*54fd6939SJiyong Park# 39*54fd6939SJiyong Park# If SCP firmware will always be present (or absent), the unused implementation 40*54fd6939SJiyong Park# can be compiled out. 41*54fd6939SJiyong ParkSUNXI_PSCI_USE_NATIVE ?= 1 42*54fd6939SJiyong ParkSUNXI_PSCI_USE_SCPI ?= 1 43*54fd6939SJiyong Park 44*54fd6939SJiyong Park$(eval $(call assert_boolean,SUNXI_PSCI_USE_NATIVE)) 45*54fd6939SJiyong Park$(eval $(call assert_boolean,SUNXI_PSCI_USE_SCPI)) 46*54fd6939SJiyong Park$(eval $(call add_define,SUNXI_PSCI_USE_NATIVE)) 47*54fd6939SJiyong Park$(eval $(call add_define,SUNXI_PSCI_USE_SCPI)) 48*54fd6939SJiyong Park 49*54fd6939SJiyong Parkifeq (${SUNXI_PSCI_USE_NATIVE}${SUNXI_PSCI_USE_SCPI},00) 50*54fd6939SJiyong Park$(error "At least one of SCPI or native PSCI ops must be enabled") 51*54fd6939SJiyong Parkendif 52*54fd6939SJiyong Park 53*54fd6939SJiyong Parkifeq (${SUNXI_PSCI_USE_NATIVE},1) 54*54fd6939SJiyong ParkBL31_SOURCES += ${AW_PLAT}/common/sunxi_cpu_ops.c \ 55*54fd6939SJiyong Park ${AW_PLAT}/common/sunxi_native_pm.c 56*54fd6939SJiyong Parkendif 57*54fd6939SJiyong Park 58*54fd6939SJiyong Parkifeq (${SUNXI_PSCI_USE_SCPI},1) 59*54fd6939SJiyong ParkBL31_SOURCES += drivers/allwinner/sunxi_msgbox.c \ 60*54fd6939SJiyong Park drivers/arm/css/scpi/css_scpi.c \ 61*54fd6939SJiyong Park ${AW_PLAT}/common/sunxi_scpi_pm.c 62*54fd6939SJiyong Parkendif 63*54fd6939SJiyong Park 64*54fd6939SJiyong Park# The bootloader is guaranteed to only run on CPU 0 by the boot ROM. 65*54fd6939SJiyong ParkCOLD_BOOT_SINGLE_CPU := 1 66*54fd6939SJiyong Park 67*54fd6939SJiyong Park# Do not enable SPE (not supported on ARM v8.0). 68*54fd6939SJiyong ParkENABLE_SPE_FOR_LOWER_ELS := 0 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park# Do not enable SVE (not supported on ARM v8.0). 71*54fd6939SJiyong ParkENABLE_SVE_FOR_NS := 0 72*54fd6939SJiyong Park 73*54fd6939SJiyong Park# Enable workarounds for Cortex-A53 errata. Allwinner uses at least r0p4. 74*54fd6939SJiyong ParkERRATA_A53_835769 := 1 75*54fd6939SJiyong ParkERRATA_A53_843419 := 1 76*54fd6939SJiyong ParkERRATA_A53_855873 := 1 77*54fd6939SJiyong ParkERRATA_A53_1530924 := 1 78*54fd6939SJiyong Park 79*54fd6939SJiyong Park# The traditional U-Boot load address is 160MB into DRAM. 80*54fd6939SJiyong ParkPRELOADED_BL33_BASE ?= 0x4a000000 81*54fd6939SJiyong Park 82*54fd6939SJiyong Park# The reset vector can be changed for each CPU. 83*54fd6939SJiyong ParkPROGRAMMABLE_RESET_ADDRESS := 1 84*54fd6939SJiyong Park 85*54fd6939SJiyong Park# Allow mapping read-only data as execute-never. 86*54fd6939SJiyong ParkSEPARATE_CODE_AND_RODATA := 1 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL 89*54fd6939SJiyong ParkRESET_TO_BL31 := 1 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park# This platform is single-cluster and does not require coherency setup. 92*54fd6939SJiyong ParkWARMBOOT_ENABLE_DCACHE_EARLY := 1 93