1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park#include <arch.h> 7*54fd6939SJiyong Park#include <asm_macros.S> 8*54fd6939SJiyong Park#include <cpu_macros.S> 9*54fd6939SJiyong Park#include <qemu_max.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Parkfunc qemu_max_core_pwr_dwn 12*54fd6939SJiyong Park /* --------------------------------------------- 13*54fd6939SJiyong Park * Disable the Data Cache. 14*54fd6939SJiyong Park * --------------------------------------------- 15*54fd6939SJiyong Park */ 16*54fd6939SJiyong Park mrs x1, sctlr_el3 17*54fd6939SJiyong Park bic x1, x1, #SCTLR_C_BIT 18*54fd6939SJiyong Park msr sctlr_el3, x1 19*54fd6939SJiyong Park isb 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park /* --------------------------------------------- 22*54fd6939SJiyong Park * Flush L1 cache to L2. 23*54fd6939SJiyong Park * --------------------------------------------- 24*54fd6939SJiyong Park */ 25*54fd6939SJiyong Park mov x18, lr 26*54fd6939SJiyong Park mov x0, #DCCISW 27*54fd6939SJiyong Park bl dcsw_op_level1 28*54fd6939SJiyong Park mov lr, x18 29*54fd6939SJiyong Park ret 30*54fd6939SJiyong Parkendfunc qemu_max_core_pwr_dwn 31*54fd6939SJiyong Park 32*54fd6939SJiyong Parkfunc qemu_max_cluster_pwr_dwn 33*54fd6939SJiyong Park /* --------------------------------------------- 34*54fd6939SJiyong Park * Disable the Data Cache. 35*54fd6939SJiyong Park * --------------------------------------------- 36*54fd6939SJiyong Park */ 37*54fd6939SJiyong Park mrs x1, sctlr_el3 38*54fd6939SJiyong Park bic x1, x1, #SCTLR_C_BIT 39*54fd6939SJiyong Park msr sctlr_el3, x1 40*54fd6939SJiyong Park isb 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park /* --------------------------------------------- 43*54fd6939SJiyong Park * Flush all caches to PoC. 44*54fd6939SJiyong Park * --------------------------------------------- 45*54fd6939SJiyong Park */ 46*54fd6939SJiyong Park mov x0, #DCCISW 47*54fd6939SJiyong Park b dcsw_op_all 48*54fd6939SJiyong Parkendfunc qemu_max_cluster_pwr_dwn 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park#if REPORT_ERRATA 51*54fd6939SJiyong Park/* 52*54fd6939SJiyong Park * Errata printing function for QEMU "max". Must follow AAPCS. 53*54fd6939SJiyong Park */ 54*54fd6939SJiyong Parkfunc qemu_max_errata_report 55*54fd6939SJiyong Park ret 56*54fd6939SJiyong Parkendfunc qemu_max_errata_report 57*54fd6939SJiyong Park#endif 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park /* --------------------------------------------- 60*54fd6939SJiyong Park * This function provides cpu specific 61*54fd6939SJiyong Park * register information for crash reporting. 62*54fd6939SJiyong Park * It needs to return with x6 pointing to 63*54fd6939SJiyong Park * a list of register names in ascii and 64*54fd6939SJiyong Park * x8 - x15 having values of registers to be 65*54fd6939SJiyong Park * reported. 66*54fd6939SJiyong Park * --------------------------------------------- 67*54fd6939SJiyong Park */ 68*54fd6939SJiyong Park.section .rodata.qemu_max_regs, "aS" 69*54fd6939SJiyong Parkqemu_max_regs: /* The ascii list of register names to be reported */ 70*54fd6939SJiyong Park .asciz "" /* no registers to report */ 71*54fd6939SJiyong Park 72*54fd6939SJiyong Parkfunc qemu_max_cpu_reg_dump 73*54fd6939SJiyong Park adr x6, qemu_max_regs 74*54fd6939SJiyong Park ret 75*54fd6939SJiyong Parkendfunc qemu_max_cpu_reg_dump 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park/* cpu_ops for QEMU MAX */ 79*54fd6939SJiyong Parkdeclare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \ 80*54fd6939SJiyong Park qemu_max_core_pwr_dwn, \ 81*54fd6939SJiyong Park qemu_max_cluster_pwr_dwn 82