xref: /aosp_15_r20/external/arm-trusted-firmware/lib/cpus/aarch64/neoverse_e1.S (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park/*
2*54fd6939SJiyong Park * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
3*54fd6939SJiyong Park *
4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park */
6*54fd6939SJiyong Park#include <arch.h>
7*54fd6939SJiyong Park#include <asm_macros.S>
8*54fd6939SJiyong Park#include <common/bl_common.h>
9*54fd6939SJiyong Park#include <common/debug.h>
10*54fd6939SJiyong Park#include <neoverse_e1.h>
11*54fd6939SJiyong Park#include <cpu_macros.S>
12*54fd6939SJiyong Park#include <plat_macros.S>
13*54fd6939SJiyong Park
14*54fd6939SJiyong Park/* Hardware handled coherency */
15*54fd6939SJiyong Park#if HW_ASSISTED_COHERENCY == 0
16*54fd6939SJiyong Park#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
17*54fd6939SJiyong Park#endif
18*54fd6939SJiyong Park
19*54fd6939SJiyong Park/* 64-bit only core */
20*54fd6939SJiyong Park#if CTX_INCLUDE_AARCH32_REGS == 1
21*54fd6939SJiyong Park#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22*54fd6939SJiyong Park#endif
23*54fd6939SJiyong Park
24*54fd6939SJiyong Park	/* -------------------------------------------------
25*54fd6939SJiyong Park	 * The CPU Ops reset function for Neoverse-E1.
26*54fd6939SJiyong Park	 * Shall clobber: x0-x19
27*54fd6939SJiyong Park	 * -------------------------------------------------
28*54fd6939SJiyong Park	 */
29*54fd6939SJiyong Parkfunc neoverse_e1_reset_func
30*54fd6939SJiyong Park	mov	x19, x30
31*54fd6939SJiyong Park
32*54fd6939SJiyong Park#if ERRATA_DSU_936184
33*54fd6939SJiyong Park	bl	errata_dsu_936184_wa
34*54fd6939SJiyong Park#endif
35*54fd6939SJiyong Park
36*54fd6939SJiyong Park	ret	x19
37*54fd6939SJiyong Parkendfunc neoverse_e1_reset_func
38*54fd6939SJiyong Park
39*54fd6939SJiyong Parkfunc neoverse_e1_cpu_pwr_dwn
40*54fd6939SJiyong Park	mrs	x0, NEOVERSE_E1_CPUPWRCTLR_EL1
41*54fd6939SJiyong Park	orr	x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
42*54fd6939SJiyong Park	msr	NEOVERSE_E1_CPUPWRCTLR_EL1, x0
43*54fd6939SJiyong Park	isb
44*54fd6939SJiyong Park	ret
45*54fd6939SJiyong Parkendfunc neoverse_e1_cpu_pwr_dwn
46*54fd6939SJiyong Park
47*54fd6939SJiyong Park#if REPORT_ERRATA
48*54fd6939SJiyong Park/*
49*54fd6939SJiyong Park * Errata printing function for Neoverse N1. Must follow AAPCS.
50*54fd6939SJiyong Park */
51*54fd6939SJiyong Parkfunc neoverse_e1_errata_report
52*54fd6939SJiyong Park	stp	x8, x30, [sp, #-16]!
53*54fd6939SJiyong Park
54*54fd6939SJiyong Park	bl	cpu_get_rev_var
55*54fd6939SJiyong Park	mov	x8, x0
56*54fd6939SJiyong Park
57*54fd6939SJiyong Park	/*
58*54fd6939SJiyong Park	 * Report all errata. The revision-variant information is passed to
59*54fd6939SJiyong Park	 * checking functions of each errata.
60*54fd6939SJiyong Park	 */
61*54fd6939SJiyong Park	report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
62*54fd6939SJiyong Park
63*54fd6939SJiyong Park	ldp	x8, x30, [sp], #16
64*54fd6939SJiyong Park	ret
65*54fd6939SJiyong Parkendfunc neoverse_e1_errata_report
66*54fd6939SJiyong Park#endif
67*54fd6939SJiyong Park
68*54fd6939SJiyong Park
69*54fd6939SJiyong Park.section .rodata.neoverse_e1_regs, "aS"
70*54fd6939SJiyong Parkneoverse_e1_regs:  /* The ascii list of register names to be reported */
71*54fd6939SJiyong Park	.asciz	"cpuectlr_el1", ""
72*54fd6939SJiyong Park
73*54fd6939SJiyong Parkfunc neoverse_e1_cpu_reg_dump
74*54fd6939SJiyong Park	adr	x6, neoverse_e1_regs
75*54fd6939SJiyong Park	mrs	x8, NEOVERSE_E1_ECTLR_EL1
76*54fd6939SJiyong Park	ret
77*54fd6939SJiyong Parkendfunc neoverse_e1_cpu_reg_dump
78*54fd6939SJiyong Park
79*54fd6939SJiyong Parkdeclare_cpu_ops neoverse_e1, NEOVERSE_E1_MIDR, \
80*54fd6939SJiyong Park	neoverse_e1_reset_func, \
81*54fd6939SJiyong Park	neoverse_e1_cpu_pwr_dwn
82