1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2020, Arm Limited. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <common/bl_common.h> 10*54fd6939SJiyong Park#include <generic.h> 11*54fd6939SJiyong Park#include <cpu_macros.S> 12*54fd6939SJiyong Park#include <plat_macros.S> 13*54fd6939SJiyong Park 14*54fd6939SJiyong Park /* --------------------------------------------- 15*54fd6939SJiyong Park * Disable L1 data cache and unified L2 cache 16*54fd6939SJiyong Park * --------------------------------------------- 17*54fd6939SJiyong Park */ 18*54fd6939SJiyong Parkfunc generic_disable_dcache 19*54fd6939SJiyong Park mrs x1, sctlr_el3 20*54fd6939SJiyong Park bic x1, x1, #SCTLR_C_BIT 21*54fd6939SJiyong Park msr sctlr_el3, x1 22*54fd6939SJiyong Park isb 23*54fd6939SJiyong Park ret 24*54fd6939SJiyong Parkendfunc generic_disable_dcache 25*54fd6939SJiyong Park 26*54fd6939SJiyong Parkfunc generic_core_pwr_dwn 27*54fd6939SJiyong Park mov x18, x30 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park /* --------------------------------------------- 30*54fd6939SJiyong Park * Turn off caches. 31*54fd6939SJiyong Park * --------------------------------------------- 32*54fd6939SJiyong Park */ 33*54fd6939SJiyong Park bl generic_disable_dcache 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park /* --------------------------------------------- 36*54fd6939SJiyong Park * Flush L1 caches. 37*54fd6939SJiyong Park * --------------------------------------------- 38*54fd6939SJiyong Park */ 39*54fd6939SJiyong Park mov x0, #DCCISW 40*54fd6939SJiyong Park bl dcsw_op_level1 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park ret x18 43*54fd6939SJiyong Parkendfunc generic_core_pwr_dwn 44*54fd6939SJiyong Park 45*54fd6939SJiyong Parkfunc generic_cluster_pwr_dwn 46*54fd6939SJiyong Park mov x18, x30 47*54fd6939SJiyong Park 48*54fd6939SJiyong Park /* --------------------------------------------- 49*54fd6939SJiyong Park * Turn off caches. 50*54fd6939SJiyong Park * --------------------------------------------- 51*54fd6939SJiyong Park */ 52*54fd6939SJiyong Park bl generic_disable_dcache 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park /* --------------------------------------------- 55*54fd6939SJiyong Park * Flush L1 caches. 56*54fd6939SJiyong Park * --------------------------------------------- 57*54fd6939SJiyong Park */ 58*54fd6939SJiyong Park mov x0, #DCCISW 59*54fd6939SJiyong Park bl dcsw_op_level1 60*54fd6939SJiyong Park 61*54fd6939SJiyong Park /* --------------------------------------------- 62*54fd6939SJiyong Park * Disable the optional ACP. 63*54fd6939SJiyong Park * --------------------------------------------- 64*54fd6939SJiyong Park */ 65*54fd6939SJiyong Park bl plat_disable_acp 66*54fd6939SJiyong Park 67*54fd6939SJiyong Park /* --------------------------------------------- 68*54fd6939SJiyong Park * Flush L2 caches. 69*54fd6939SJiyong Park * --------------------------------------------- 70*54fd6939SJiyong Park */ 71*54fd6939SJiyong Park mov x0, #DCCISW 72*54fd6939SJiyong Park bl dcsw_op_level2 73*54fd6939SJiyong Park 74*54fd6939SJiyong Park ret x18 75*54fd6939SJiyong Park 76*54fd6939SJiyong Parkendfunc generic_cluster_pwr_dwn 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park/* --------------------------------------------- 79*54fd6939SJiyong Park * Unimplemented functions. 80*54fd6939SJiyong Park * --------------------------------------------- 81*54fd6939SJiyong Park */ 82*54fd6939SJiyong Park.equ generic_errata_report, 0 83*54fd6939SJiyong Park.equ generic_cpu_reg_dump, 0 84*54fd6939SJiyong Park.equ generic_reset_func, 0 85*54fd6939SJiyong Park 86*54fd6939SJiyong Parkdeclare_cpu_ops generic, AARCH64_GENERIC_MIDR, \ 87*54fd6939SJiyong Park generic_reset_func, \ 88*54fd6939SJiyong Park generic_core_pwr_dwn, \ 89*54fd6939SJiyong Park generic_cluster_pwr_dwn 90