1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4*54fd6939SJiyong Park * 5*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park#include <arch.h> 9*54fd6939SJiyong Park#include <asm_macros.S> 10*54fd6939SJiyong Park#include <assert_macros.S> 11*54fd6939SJiyong Park#include <context.h> 12*54fd6939SJiyong Park#include <denver.h> 13*54fd6939SJiyong Park#include <cpu_macros.S> 14*54fd6939SJiyong Park#include <plat_macros.S> 15*54fd6939SJiyong Park 16*54fd6939SJiyong Park /* ------------------------------------------------- 17*54fd6939SJiyong Park * CVE-2017-5715 mitigation 18*54fd6939SJiyong Park * 19*54fd6939SJiyong Park * Flush the indirect branch predictor and RSB on 20*54fd6939SJiyong Park * entry to EL3 by issuing a newly added instruction 21*54fd6939SJiyong Park * for Denver CPUs. 22*54fd6939SJiyong Park * 23*54fd6939SJiyong Park * To achieve this without performing any branch 24*54fd6939SJiyong Park * instruction, a per-cpu vbar is installed which 25*54fd6939SJiyong Park * executes the workaround and then branches off to 26*54fd6939SJiyong Park * the corresponding vector entry in the main vector 27*54fd6939SJiyong Park * table. 28*54fd6939SJiyong Park * ------------------------------------------------- 29*54fd6939SJiyong Park */ 30*54fd6939SJiyong Parkvector_base workaround_bpflush_runtime_exceptions 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park .macro apply_workaround 33*54fd6939SJiyong Park stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park /* Disable cycle counter when event counting is prohibited */ 36*54fd6939SJiyong Park mrs x1, pmcr_el0 37*54fd6939SJiyong Park orr x0, x1, #PMCR_EL0_DP_BIT 38*54fd6939SJiyong Park msr pmcr_el0, x0 39*54fd6939SJiyong Park isb 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park /* ------------------------------------------------- 42*54fd6939SJiyong Park * A new write-only system register where a write of 43*54fd6939SJiyong Park * 1 to bit 0 will cause the indirect branch predictor 44*54fd6939SJiyong Park * and RSB to be flushed. 45*54fd6939SJiyong Park * 46*54fd6939SJiyong Park * A write of 0 to bit 0 will be ignored. A write of 47*54fd6939SJiyong Park * 1 to any other bit will cause an MCA. 48*54fd6939SJiyong Park * ------------------------------------------------- 49*54fd6939SJiyong Park */ 50*54fd6939SJiyong Park mov x0, #1 51*54fd6939SJiyong Park msr s3_0_c15_c0_6, x0 52*54fd6939SJiyong Park isb 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 55*54fd6939SJiyong Park .endm 56*54fd6939SJiyong Park 57*54fd6939SJiyong Park /* --------------------------------------------------------------------- 58*54fd6939SJiyong Park * Current EL with SP_EL0 : 0x0 - 0x200 59*54fd6939SJiyong Park * --------------------------------------------------------------------- 60*54fd6939SJiyong Park */ 61*54fd6939SJiyong Parkvector_entry workaround_bpflush_sync_exception_sp_el0 62*54fd6939SJiyong Park b sync_exception_sp_el0 63*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_sync_exception_sp_el0 64*54fd6939SJiyong Park 65*54fd6939SJiyong Parkvector_entry workaround_bpflush_irq_sp_el0 66*54fd6939SJiyong Park b irq_sp_el0 67*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_irq_sp_el0 68*54fd6939SJiyong Park 69*54fd6939SJiyong Parkvector_entry workaround_bpflush_fiq_sp_el0 70*54fd6939SJiyong Park b fiq_sp_el0 71*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_fiq_sp_el0 72*54fd6939SJiyong Park 73*54fd6939SJiyong Parkvector_entry workaround_bpflush_serror_sp_el0 74*54fd6939SJiyong Park b serror_sp_el0 75*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_serror_sp_el0 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park /* --------------------------------------------------------------------- 78*54fd6939SJiyong Park * Current EL with SP_ELx: 0x200 - 0x400 79*54fd6939SJiyong Park * --------------------------------------------------------------------- 80*54fd6939SJiyong Park */ 81*54fd6939SJiyong Parkvector_entry workaround_bpflush_sync_exception_sp_elx 82*54fd6939SJiyong Park b sync_exception_sp_elx 83*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_sync_exception_sp_elx 84*54fd6939SJiyong Park 85*54fd6939SJiyong Parkvector_entry workaround_bpflush_irq_sp_elx 86*54fd6939SJiyong Park b irq_sp_elx 87*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_irq_sp_elx 88*54fd6939SJiyong Park 89*54fd6939SJiyong Parkvector_entry workaround_bpflush_fiq_sp_elx 90*54fd6939SJiyong Park b fiq_sp_elx 91*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_fiq_sp_elx 92*54fd6939SJiyong Park 93*54fd6939SJiyong Parkvector_entry workaround_bpflush_serror_sp_elx 94*54fd6939SJiyong Park b serror_sp_elx 95*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_serror_sp_elx 96*54fd6939SJiyong Park 97*54fd6939SJiyong Park /* --------------------------------------------------------------------- 98*54fd6939SJiyong Park * Lower EL using AArch64 : 0x400 - 0x600 99*54fd6939SJiyong Park * --------------------------------------------------------------------- 100*54fd6939SJiyong Park */ 101*54fd6939SJiyong Parkvector_entry workaround_bpflush_sync_exception_aarch64 102*54fd6939SJiyong Park apply_workaround 103*54fd6939SJiyong Park b sync_exception_aarch64 104*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_sync_exception_aarch64 105*54fd6939SJiyong Park 106*54fd6939SJiyong Parkvector_entry workaround_bpflush_irq_aarch64 107*54fd6939SJiyong Park apply_workaround 108*54fd6939SJiyong Park b irq_aarch64 109*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_irq_aarch64 110*54fd6939SJiyong Park 111*54fd6939SJiyong Parkvector_entry workaround_bpflush_fiq_aarch64 112*54fd6939SJiyong Park apply_workaround 113*54fd6939SJiyong Park b fiq_aarch64 114*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_fiq_aarch64 115*54fd6939SJiyong Park 116*54fd6939SJiyong Parkvector_entry workaround_bpflush_serror_aarch64 117*54fd6939SJiyong Park apply_workaround 118*54fd6939SJiyong Park b serror_aarch64 119*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_serror_aarch64 120*54fd6939SJiyong Park 121*54fd6939SJiyong Park /* --------------------------------------------------------------------- 122*54fd6939SJiyong Park * Lower EL using AArch32 : 0x600 - 0x800 123*54fd6939SJiyong Park * --------------------------------------------------------------------- 124*54fd6939SJiyong Park */ 125*54fd6939SJiyong Parkvector_entry workaround_bpflush_sync_exception_aarch32 126*54fd6939SJiyong Park apply_workaround 127*54fd6939SJiyong Park b sync_exception_aarch32 128*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_sync_exception_aarch32 129*54fd6939SJiyong Park 130*54fd6939SJiyong Parkvector_entry workaround_bpflush_irq_aarch32 131*54fd6939SJiyong Park apply_workaround 132*54fd6939SJiyong Park b irq_aarch32 133*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_irq_aarch32 134*54fd6939SJiyong Park 135*54fd6939SJiyong Parkvector_entry workaround_bpflush_fiq_aarch32 136*54fd6939SJiyong Park apply_workaround 137*54fd6939SJiyong Park b fiq_aarch32 138*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_fiq_aarch32 139*54fd6939SJiyong Park 140*54fd6939SJiyong Parkvector_entry workaround_bpflush_serror_aarch32 141*54fd6939SJiyong Park apply_workaround 142*54fd6939SJiyong Park b serror_aarch32 143*54fd6939SJiyong Parkend_vector_entry workaround_bpflush_serror_aarch32 144*54fd6939SJiyong Park 145*54fd6939SJiyong Park .global denver_disable_dco 146*54fd6939SJiyong Park 147*54fd6939SJiyong Park /* --------------------------------------------- 148*54fd6939SJiyong Park * Disable debug interfaces 149*54fd6939SJiyong Park * --------------------------------------------- 150*54fd6939SJiyong Park */ 151*54fd6939SJiyong Parkfunc denver_disable_ext_debug 152*54fd6939SJiyong Park mov x0, #1 153*54fd6939SJiyong Park msr osdlr_el1, x0 154*54fd6939SJiyong Park isb 155*54fd6939SJiyong Park dsb sy 156*54fd6939SJiyong Park ret 157*54fd6939SJiyong Parkendfunc denver_disable_ext_debug 158*54fd6939SJiyong Park 159*54fd6939SJiyong Park /* ---------------------------------------------------- 160*54fd6939SJiyong Park * Enable dynamic code optimizer (DCO) 161*54fd6939SJiyong Park * ---------------------------------------------------- 162*54fd6939SJiyong Park */ 163*54fd6939SJiyong Parkfunc denver_enable_dco 164*54fd6939SJiyong Park /* DCO is not supported on PN5 and later */ 165*54fd6939SJiyong Park mrs x1, midr_el1 166*54fd6939SJiyong Park mov_imm x2, DENVER_MIDR_PN4 167*54fd6939SJiyong Park cmp x1, x2 168*54fd6939SJiyong Park b.hi 1f 169*54fd6939SJiyong Park 170*54fd6939SJiyong Park mov x18, x30 171*54fd6939SJiyong Park bl plat_my_core_pos 172*54fd6939SJiyong Park mov x1, #1 173*54fd6939SJiyong Park lsl x1, x1, x0 174*54fd6939SJiyong Park msr s3_0_c15_c0_2, x1 175*54fd6939SJiyong Park mov x30, x18 176*54fd6939SJiyong Park1: ret 177*54fd6939SJiyong Parkendfunc denver_enable_dco 178*54fd6939SJiyong Park 179*54fd6939SJiyong Park /* ---------------------------------------------------- 180*54fd6939SJiyong Park * Disable dynamic code optimizer (DCO) 181*54fd6939SJiyong Park * ---------------------------------------------------- 182*54fd6939SJiyong Park */ 183*54fd6939SJiyong Parkfunc denver_disable_dco 184*54fd6939SJiyong Park /* DCO is not supported on PN5 and later */ 185*54fd6939SJiyong Park mrs x1, midr_el1 186*54fd6939SJiyong Park mov_imm x2, DENVER_MIDR_PN4 187*54fd6939SJiyong Park cmp x1, x2 188*54fd6939SJiyong Park b.hi 2f 189*54fd6939SJiyong Park 190*54fd6939SJiyong Park /* turn off background work */ 191*54fd6939SJiyong Park mov x18, x30 192*54fd6939SJiyong Park bl plat_my_core_pos 193*54fd6939SJiyong Park mov x1, #1 194*54fd6939SJiyong Park lsl x1, x1, x0 195*54fd6939SJiyong Park lsl x2, x1, #16 196*54fd6939SJiyong Park msr s3_0_c15_c0_2, x2 197*54fd6939SJiyong Park isb 198*54fd6939SJiyong Park 199*54fd6939SJiyong Park /* wait till the background work turns off */ 200*54fd6939SJiyong Park1: mrs x2, s3_0_c15_c0_2 201*54fd6939SJiyong Park lsr x2, x2, #32 202*54fd6939SJiyong Park and w2, w2, 0xFFFF 203*54fd6939SJiyong Park and x2, x2, x1 204*54fd6939SJiyong Park cbnz x2, 1b 205*54fd6939SJiyong Park 206*54fd6939SJiyong Park mov x30, x18 207*54fd6939SJiyong Park2: ret 208*54fd6939SJiyong Parkendfunc denver_disable_dco 209*54fd6939SJiyong Park 210*54fd6939SJiyong Parkfunc check_errata_cve_2017_5715 211*54fd6939SJiyong Park mov x0, #ERRATA_MISSING 212*54fd6939SJiyong Park#if WORKAROUND_CVE_2017_5715 213*54fd6939SJiyong Park /* 214*54fd6939SJiyong Park * Check if the CPU supports the special instruction 215*54fd6939SJiyong Park * required to flush the indirect branch predictor and 216*54fd6939SJiyong Park * RSB. Support for this operation can be determined by 217*54fd6939SJiyong Park * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. 218*54fd6939SJiyong Park */ 219*54fd6939SJiyong Park mrs x1, id_afr0_el1 220*54fd6939SJiyong Park mov x2, #0x10000 221*54fd6939SJiyong Park and x1, x1, x2 222*54fd6939SJiyong Park cbz x1, 1f 223*54fd6939SJiyong Park mov x0, #ERRATA_APPLIES 224*54fd6939SJiyong Park1: 225*54fd6939SJiyong Park#endif 226*54fd6939SJiyong Park ret 227*54fd6939SJiyong Parkendfunc check_errata_cve_2017_5715 228*54fd6939SJiyong Park 229*54fd6939SJiyong Parkfunc check_errata_cve_2018_3639 230*54fd6939SJiyong Park#if WORKAROUND_CVE_2018_3639 231*54fd6939SJiyong Park mov x0, #ERRATA_APPLIES 232*54fd6939SJiyong Park#else 233*54fd6939SJiyong Park mov x0, #ERRATA_MISSING 234*54fd6939SJiyong Park#endif 235*54fd6939SJiyong Park ret 236*54fd6939SJiyong Parkendfunc check_errata_cve_2018_3639 237*54fd6939SJiyong Park 238*54fd6939SJiyong Park /* ------------------------------------------------- 239*54fd6939SJiyong Park * The CPU Ops reset function for Denver. 240*54fd6939SJiyong Park * ------------------------------------------------- 241*54fd6939SJiyong Park */ 242*54fd6939SJiyong Parkfunc denver_reset_func 243*54fd6939SJiyong Park 244*54fd6939SJiyong Park mov x19, x30 245*54fd6939SJiyong Park 246*54fd6939SJiyong Park#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 247*54fd6939SJiyong Park /* 248*54fd6939SJiyong Park * Check if the CPU supports the special instruction 249*54fd6939SJiyong Park * required to flush the indirect branch predictor and 250*54fd6939SJiyong Park * RSB. Support for this operation can be determined by 251*54fd6939SJiyong Park * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. 252*54fd6939SJiyong Park */ 253*54fd6939SJiyong Park mrs x0, id_afr0_el1 254*54fd6939SJiyong Park mov x1, #0x10000 255*54fd6939SJiyong Park and x0, x0, x1 256*54fd6939SJiyong Park cmp x0, #0 257*54fd6939SJiyong Park adr x1, workaround_bpflush_runtime_exceptions 258*54fd6939SJiyong Park mrs x2, vbar_el3 259*54fd6939SJiyong Park csel x0, x1, x2, ne 260*54fd6939SJiyong Park msr vbar_el3, x0 261*54fd6939SJiyong Park#endif 262*54fd6939SJiyong Park 263*54fd6939SJiyong Park#if WORKAROUND_CVE_2018_3639 264*54fd6939SJiyong Park /* 265*54fd6939SJiyong Park * Denver CPUs with DENVER_MIDR_PN3 or earlier, use different 266*54fd6939SJiyong Park * bits in the ACTLR_EL3 register to disable speculative 267*54fd6939SJiyong Park * store buffer and memory disambiguation. 268*54fd6939SJiyong Park */ 269*54fd6939SJiyong Park mrs x0, midr_el1 270*54fd6939SJiyong Park mov_imm x1, DENVER_MIDR_PN4 271*54fd6939SJiyong Park cmp x0, x1 272*54fd6939SJiyong Park mrs x0, actlr_el3 273*54fd6939SJiyong Park mov x1, #(DENVER_CPU_DIS_MD_EL3 | DENVER_CPU_DIS_SSB_EL3) 274*54fd6939SJiyong Park mov x2, #(DENVER_PN4_CPU_DIS_MD_EL3 | DENVER_PN4_CPU_DIS_SSB_EL3) 275*54fd6939SJiyong Park csel x3, x1, x2, ne 276*54fd6939SJiyong Park orr x0, x0, x3 277*54fd6939SJiyong Park msr actlr_el3, x0 278*54fd6939SJiyong Park isb 279*54fd6939SJiyong Park dsb sy 280*54fd6939SJiyong Park#endif 281*54fd6939SJiyong Park 282*54fd6939SJiyong Park /* ---------------------------------------------------- 283*54fd6939SJiyong Park * Reset ACTLR.PMSTATE to C1 state 284*54fd6939SJiyong Park * ---------------------------------------------------- 285*54fd6939SJiyong Park */ 286*54fd6939SJiyong Park mrs x0, actlr_el1 287*54fd6939SJiyong Park bic x0, x0, #DENVER_CPU_PMSTATE_MASK 288*54fd6939SJiyong Park orr x0, x0, #DENVER_CPU_PMSTATE_C1 289*54fd6939SJiyong Park msr actlr_el1, x0 290*54fd6939SJiyong Park 291*54fd6939SJiyong Park /* ---------------------------------------------------- 292*54fd6939SJiyong Park * Enable dynamic code optimizer (DCO) 293*54fd6939SJiyong Park * ---------------------------------------------------- 294*54fd6939SJiyong Park */ 295*54fd6939SJiyong Park bl denver_enable_dco 296*54fd6939SJiyong Park 297*54fd6939SJiyong Park ret x19 298*54fd6939SJiyong Parkendfunc denver_reset_func 299*54fd6939SJiyong Park 300*54fd6939SJiyong Park /* ---------------------------------------------------- 301*54fd6939SJiyong Park * The CPU Ops core power down function for Denver. 302*54fd6939SJiyong Park * ---------------------------------------------------- 303*54fd6939SJiyong Park */ 304*54fd6939SJiyong Parkfunc denver_core_pwr_dwn 305*54fd6939SJiyong Park 306*54fd6939SJiyong Park mov x19, x30 307*54fd6939SJiyong Park 308*54fd6939SJiyong Park /* --------------------------------------------- 309*54fd6939SJiyong Park * Force the debug interfaces to be quiescent 310*54fd6939SJiyong Park * --------------------------------------------- 311*54fd6939SJiyong Park */ 312*54fd6939SJiyong Park bl denver_disable_ext_debug 313*54fd6939SJiyong Park 314*54fd6939SJiyong Park ret x19 315*54fd6939SJiyong Parkendfunc denver_core_pwr_dwn 316*54fd6939SJiyong Park 317*54fd6939SJiyong Park /* ------------------------------------------------------- 318*54fd6939SJiyong Park * The CPU Ops cluster power down function for Denver. 319*54fd6939SJiyong Park * ------------------------------------------------------- 320*54fd6939SJiyong Park */ 321*54fd6939SJiyong Parkfunc denver_cluster_pwr_dwn 322*54fd6939SJiyong Park ret 323*54fd6939SJiyong Parkendfunc denver_cluster_pwr_dwn 324*54fd6939SJiyong Park 325*54fd6939SJiyong Park#if REPORT_ERRATA 326*54fd6939SJiyong Park /* 327*54fd6939SJiyong Park * Errata printing function for Denver. Must follow AAPCS. 328*54fd6939SJiyong Park */ 329*54fd6939SJiyong Parkfunc denver_errata_report 330*54fd6939SJiyong Park stp x8, x30, [sp, #-16]! 331*54fd6939SJiyong Park 332*54fd6939SJiyong Park bl cpu_get_rev_var 333*54fd6939SJiyong Park mov x8, x0 334*54fd6939SJiyong Park 335*54fd6939SJiyong Park /* 336*54fd6939SJiyong Park * Report all errata. The revision-variant information is passed to 337*54fd6939SJiyong Park * checking functions of each errata. 338*54fd6939SJiyong Park */ 339*54fd6939SJiyong Park report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715 340*54fd6939SJiyong Park report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639 341*54fd6939SJiyong Park 342*54fd6939SJiyong Park ldp x8, x30, [sp], #16 343*54fd6939SJiyong Park ret 344*54fd6939SJiyong Parkendfunc denver_errata_report 345*54fd6939SJiyong Park#endif 346*54fd6939SJiyong Park 347*54fd6939SJiyong Park /* --------------------------------------------- 348*54fd6939SJiyong Park * This function provides Denver specific 349*54fd6939SJiyong Park * register information for crash reporting. 350*54fd6939SJiyong Park * It needs to return with x6 pointing to 351*54fd6939SJiyong Park * a list of register names in ascii and 352*54fd6939SJiyong Park * x8 - x15 having values of registers to be 353*54fd6939SJiyong Park * reported. 354*54fd6939SJiyong Park * --------------------------------------------- 355*54fd6939SJiyong Park */ 356*54fd6939SJiyong Park.section .rodata.denver_regs, "aS" 357*54fd6939SJiyong Parkdenver_regs: /* The ascii list of register names to be reported */ 358*54fd6939SJiyong Park .asciz "actlr_el1", "" 359*54fd6939SJiyong Park 360*54fd6939SJiyong Parkfunc denver_cpu_reg_dump 361*54fd6939SJiyong Park adr x6, denver_regs 362*54fd6939SJiyong Park mrs x8, ACTLR_EL1 363*54fd6939SJiyong Park ret 364*54fd6939SJiyong Parkendfunc denver_cpu_reg_dump 365*54fd6939SJiyong Park 366*54fd6939SJiyong Park/* macro to declare cpu_ops for Denver SKUs */ 367*54fd6939SJiyong Park.macro denver_cpu_ops_wa midr 368*54fd6939SJiyong Park declare_cpu_ops_wa denver, \midr, \ 369*54fd6939SJiyong Park denver_reset_func, \ 370*54fd6939SJiyong Park check_errata_cve_2017_5715, \ 371*54fd6939SJiyong Park CPU_NO_EXTRA2_FUNC, \ 372*54fd6939SJiyong Park denver_core_pwr_dwn, \ 373*54fd6939SJiyong Park denver_cluster_pwr_dwn 374*54fd6939SJiyong Park.endm 375*54fd6939SJiyong Park 376*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN0 377*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN1 378*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN2 379*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN3 380*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN4 381*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN5 382*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN6 383*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN7 384*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN8 385*54fd6939SJiyong Parkdenver_cpu_ops_wa DENVER_MIDR_PN9 386