1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <cpuamu.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park .globl cpuamu_cnt_read 12*54fd6939SJiyong Park .globl cpuamu_cnt_write 13*54fd6939SJiyong Park .globl cpuamu_read_cpuamcntenset_el0 14*54fd6939SJiyong Park .globl cpuamu_read_cpuamcntenclr_el0 15*54fd6939SJiyong Park .globl cpuamu_write_cpuamcntenset_el0 16*54fd6939SJiyong Park .globl cpuamu_write_cpuamcntenclr_el0 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park/* 19*54fd6939SJiyong Park * uint64_t cpuamu_cnt_read(unsigned int idx); 20*54fd6939SJiyong Park * 21*54fd6939SJiyong Park * Given `idx`, read the corresponding AMU counter 22*54fd6939SJiyong Park * and return it in `x0`. 23*54fd6939SJiyong Park */ 24*54fd6939SJiyong Parkfunc cpuamu_cnt_read 25*54fd6939SJiyong Park adr x1, 1f 26*54fd6939SJiyong Park add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */ 27*54fd6939SJiyong Park#if ENABLE_BTI 28*54fd6939SJiyong Park add x1, x1, x0, lsl #2 /* + "bti j" instruction */ 29*54fd6939SJiyong Park#endif 30*54fd6939SJiyong Park br x1 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park1: read CPUAMEVCNTR0_EL0 33*54fd6939SJiyong Park read CPUAMEVCNTR1_EL0 34*54fd6939SJiyong Park read CPUAMEVCNTR2_EL0 35*54fd6939SJiyong Park read CPUAMEVCNTR3_EL0 36*54fd6939SJiyong Park read CPUAMEVCNTR4_EL0 37*54fd6939SJiyong Parkendfunc cpuamu_cnt_read 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park/* 40*54fd6939SJiyong Park * void cpuamu_cnt_write(unsigned int idx, uint64_t val); 41*54fd6939SJiyong Park * 42*54fd6939SJiyong Park * Given `idx`, write `val` to the corresponding AMU counter. 43*54fd6939SJiyong Park */ 44*54fd6939SJiyong Parkfunc cpuamu_cnt_write 45*54fd6939SJiyong Park adr x2, 1f 46*54fd6939SJiyong Park add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */ 47*54fd6939SJiyong Park#if ENABLE_BTI 48*54fd6939SJiyong Park add x2, x2, x0, lsl #2 /* + "bti j" instruction */ 49*54fd6939SJiyong Park#endif 50*54fd6939SJiyong Park br x2 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park1: write CPUAMEVCNTR0_EL0 53*54fd6939SJiyong Park write CPUAMEVCNTR1_EL0 54*54fd6939SJiyong Park write CPUAMEVCNTR2_EL0 55*54fd6939SJiyong Park write CPUAMEVCNTR3_EL0 56*54fd6939SJiyong Park write CPUAMEVCNTR4_EL0 57*54fd6939SJiyong Parkendfunc cpuamu_cnt_write 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park/* 60*54fd6939SJiyong Park * unsigned int cpuamu_read_cpuamcntenset_el0(void); 61*54fd6939SJiyong Park * 62*54fd6939SJiyong Park * Read the `CPUAMCNTENSET_EL0` CPU register and return 63*54fd6939SJiyong Park * it in `x0`. 64*54fd6939SJiyong Park */ 65*54fd6939SJiyong Parkfunc cpuamu_read_cpuamcntenset_el0 66*54fd6939SJiyong Park mrs x0, CPUAMCNTENSET_EL0 67*54fd6939SJiyong Park ret 68*54fd6939SJiyong Parkendfunc cpuamu_read_cpuamcntenset_el0 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park/* 71*54fd6939SJiyong Park * unsigned int cpuamu_read_cpuamcntenclr_el0(void); 72*54fd6939SJiyong Park * 73*54fd6939SJiyong Park * Read the `CPUAMCNTENCLR_EL0` CPU register and return 74*54fd6939SJiyong Park * it in `x0`. 75*54fd6939SJiyong Park */ 76*54fd6939SJiyong Parkfunc cpuamu_read_cpuamcntenclr_el0 77*54fd6939SJiyong Park mrs x0, CPUAMCNTENCLR_EL0 78*54fd6939SJiyong Park ret 79*54fd6939SJiyong Parkendfunc cpuamu_read_cpuamcntenclr_el0 80*54fd6939SJiyong Park 81*54fd6939SJiyong Park/* 82*54fd6939SJiyong Park * void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 83*54fd6939SJiyong Park * 84*54fd6939SJiyong Park * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. 85*54fd6939SJiyong Park */ 86*54fd6939SJiyong Parkfunc cpuamu_write_cpuamcntenset_el0 87*54fd6939SJiyong Park msr CPUAMCNTENSET_EL0, x0 88*54fd6939SJiyong Park ret 89*54fd6939SJiyong Parkendfunc cpuamu_write_cpuamcntenset_el0 90*54fd6939SJiyong Park 91*54fd6939SJiyong Park/* 92*54fd6939SJiyong Park * void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 93*54fd6939SJiyong Park * 94*54fd6939SJiyong Park * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. 95*54fd6939SJiyong Park */ 96*54fd6939SJiyong Parkfunc cpuamu_write_cpuamcntenclr_el0 97*54fd6939SJiyong Park msr CPUAMCNTENCLR_EL0, x0 98*54fd6939SJiyong Park ret 99*54fd6939SJiyong Parkendfunc cpuamu_write_cpuamcntenclr_el0 100