1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park#include <aem_generic.h> 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <cpu_macros.S> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Parkfunc aem_generic_core_pwr_dwn 12*54fd6939SJiyong Park /* --------------------------------------------- 13*54fd6939SJiyong Park * Disable the Data Cache. 14*54fd6939SJiyong Park * --------------------------------------------- 15*54fd6939SJiyong Park */ 16*54fd6939SJiyong Park mrs x1, sctlr_el3 17*54fd6939SJiyong Park bic x1, x1, #SCTLR_C_BIT 18*54fd6939SJiyong Park msr sctlr_el3, x1 19*54fd6939SJiyong Park isb 20*54fd6939SJiyong Park 21*54fd6939SJiyong Park /* --------------------------------------------- 22*54fd6939SJiyong Park * AEM model supports L3 caches in which case L2 23*54fd6939SJiyong Park * will be private per core caches and flush 24*54fd6939SJiyong Park * from L1 to L2 is not sufficient. 25*54fd6939SJiyong Park * --------------------------------------------- 26*54fd6939SJiyong Park */ 27*54fd6939SJiyong Park mrs x1, clidr_el1 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park /* --------------------------------------------- 30*54fd6939SJiyong Park * Check if L3 cache is implemented. 31*54fd6939SJiyong Park * --------------------------------------------- 32*54fd6939SJiyong Park */ 33*54fd6939SJiyong Park tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3) 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park /* --------------------------------------------- 36*54fd6939SJiyong Park * There is no L3 cache, flush L1 to L2 only. 37*54fd6939SJiyong Park * --------------------------------------------- 38*54fd6939SJiyong Park */ 39*54fd6939SJiyong Park mov x0, #DCCISW 40*54fd6939SJiyong Park b.eq dcsw_op_level1 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park mov x18, x30 43*54fd6939SJiyong Park 44*54fd6939SJiyong Park /* --------------------------------------------- 45*54fd6939SJiyong Park * Flush L1 cache to L2. 46*54fd6939SJiyong Park * --------------------------------------------- 47*54fd6939SJiyong Park */ 48*54fd6939SJiyong Park bl dcsw_op_level1 49*54fd6939SJiyong Park mov x30, x18 50*54fd6939SJiyong Park 51*54fd6939SJiyong Park /* --------------------------------------------- 52*54fd6939SJiyong Park * Flush L2 cache to L3. 53*54fd6939SJiyong Park * --------------------------------------------- 54*54fd6939SJiyong Park */ 55*54fd6939SJiyong Park mov x0, #DCCISW 56*54fd6939SJiyong Park b dcsw_op_level2 57*54fd6939SJiyong Parkendfunc aem_generic_core_pwr_dwn 58*54fd6939SJiyong Park 59*54fd6939SJiyong Parkfunc aem_generic_cluster_pwr_dwn 60*54fd6939SJiyong Park /* --------------------------------------------- 61*54fd6939SJiyong Park * Disable the Data Cache. 62*54fd6939SJiyong Park * --------------------------------------------- 63*54fd6939SJiyong Park */ 64*54fd6939SJiyong Park mrs x1, sctlr_el3 65*54fd6939SJiyong Park bic x1, x1, #SCTLR_C_BIT 66*54fd6939SJiyong Park msr sctlr_el3, x1 67*54fd6939SJiyong Park isb 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park /* --------------------------------------------- 70*54fd6939SJiyong Park * Flush all caches to PoC. 71*54fd6939SJiyong Park * --------------------------------------------- 72*54fd6939SJiyong Park */ 73*54fd6939SJiyong Park mov x0, #DCCISW 74*54fd6939SJiyong Park b dcsw_op_all 75*54fd6939SJiyong Parkendfunc aem_generic_cluster_pwr_dwn 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park#if REPORT_ERRATA 78*54fd6939SJiyong Park/* 79*54fd6939SJiyong Park * Errata printing function for AEM. Must follow AAPCS. 80*54fd6939SJiyong Park */ 81*54fd6939SJiyong Parkfunc aem_generic_errata_report 82*54fd6939SJiyong Park ret 83*54fd6939SJiyong Parkendfunc aem_generic_errata_report 84*54fd6939SJiyong Park#endif 85*54fd6939SJiyong Park 86*54fd6939SJiyong Park /* --------------------------------------------- 87*54fd6939SJiyong Park * This function provides cpu specific 88*54fd6939SJiyong Park * register information for crash reporting. 89*54fd6939SJiyong Park * It needs to return with x6 pointing to 90*54fd6939SJiyong Park * a list of register names in ascii and 91*54fd6939SJiyong Park * x8 - x15 having values of registers to be 92*54fd6939SJiyong Park * reported. 93*54fd6939SJiyong Park * --------------------------------------------- 94*54fd6939SJiyong Park */ 95*54fd6939SJiyong Park.section .rodata.aem_generic_regs, "aS" 96*54fd6939SJiyong Parkaem_generic_regs: /* The ascii list of register names to be reported */ 97*54fd6939SJiyong Park .asciz "" /* no registers to report */ 98*54fd6939SJiyong Park 99*54fd6939SJiyong Parkfunc aem_generic_cpu_reg_dump 100*54fd6939SJiyong Park adr x6, aem_generic_regs 101*54fd6939SJiyong Park ret 102*54fd6939SJiyong Parkendfunc aem_generic_cpu_reg_dump 103*54fd6939SJiyong Park 104*54fd6939SJiyong Park 105*54fd6939SJiyong Park/* cpu_ops for Base AEM FVP */ 106*54fd6939SJiyong Parkdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ 107*54fd6939SJiyong Park aem_generic_core_pwr_dwn, \ 108*54fd6939SJiyong Park aem_generic_cluster_pwr_dwn 109*54fd6939SJiyong Park 110*54fd6939SJiyong Park/* cpu_ops for Foundation FVP */ 111*54fd6939SJiyong Parkdeclare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \ 112*54fd6939SJiyong Park aem_generic_core_pwr_dwn, \ 113*54fd6939SJiyong Park aem_generic_cluster_pwr_dwn 114