1*54fd6939SJiyong Park/* 2*54fd6939SJiyong Park * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park#include <aem_generic.h> 7*54fd6939SJiyong Park#include <arch.h> 8*54fd6939SJiyong Park#include <asm_macros.S> 9*54fd6939SJiyong Park#include <assert_macros.S> 10*54fd6939SJiyong Park#include <cpu_macros.S> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Parkfunc aem_generic_core_pwr_dwn 13*54fd6939SJiyong Park /* Assert if cache is enabled */ 14*54fd6939SJiyong Park#if ENABLE_ASSERTIONS 15*54fd6939SJiyong Park ldcopr r0, SCTLR 16*54fd6939SJiyong Park tst r0, #SCTLR_C_BIT 17*54fd6939SJiyong Park ASM_ASSERT(eq) 18*54fd6939SJiyong Park#endif 19*54fd6939SJiyong Park /* --------------------------------------------- 20*54fd6939SJiyong Park * Flush L1 cache to PoU. 21*54fd6939SJiyong Park * --------------------------------------------- 22*54fd6939SJiyong Park */ 23*54fd6939SJiyong Park mov r0, #DC_OP_CISW 24*54fd6939SJiyong Park b dcsw_op_louis 25*54fd6939SJiyong Parkendfunc aem_generic_core_pwr_dwn 26*54fd6939SJiyong Park 27*54fd6939SJiyong Park 28*54fd6939SJiyong Parkfunc aem_generic_cluster_pwr_dwn 29*54fd6939SJiyong Park /* Assert if cache is enabled */ 30*54fd6939SJiyong Park#if ENABLE_ASSERTIONS 31*54fd6939SJiyong Park ldcopr r0, SCTLR 32*54fd6939SJiyong Park tst r0, #SCTLR_C_BIT 33*54fd6939SJiyong Park ASM_ASSERT(eq) 34*54fd6939SJiyong Park#endif 35*54fd6939SJiyong Park /* --------------------------------------------- 36*54fd6939SJiyong Park * Flush L1 and L2 caches to PoC. 37*54fd6939SJiyong Park * --------------------------------------------- 38*54fd6939SJiyong Park */ 39*54fd6939SJiyong Park mov r0, #DC_OP_CISW 40*54fd6939SJiyong Park b dcsw_op_all 41*54fd6939SJiyong Parkendfunc aem_generic_cluster_pwr_dwn 42*54fd6939SJiyong Park 43*54fd6939SJiyong Park#if REPORT_ERRATA 44*54fd6939SJiyong Park/* 45*54fd6939SJiyong Park * Errata printing function for AEM. Must follow AAPCS. 46*54fd6939SJiyong Park */ 47*54fd6939SJiyong Parkfunc aem_generic_errata_report 48*54fd6939SJiyong Park bx lr 49*54fd6939SJiyong Parkendfunc aem_generic_errata_report 50*54fd6939SJiyong Park#endif 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park/* cpu_ops for Base AEM FVP */ 53*54fd6939SJiyong Parkdeclare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \ 54*54fd6939SJiyong Park aem_generic_core_pwr_dwn, \ 55*54fd6939SJiyong Park aem_generic_cluster_pwr_dwn 56