1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef PCI_SVC_H 8*54fd6939SJiyong Park #define PCI_SVC_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <lib/utils_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* SMCCC PCI platform functions */ 13*54fd6939SJiyong Park #define SMC_PCI_VERSION U(0x84000130) 14*54fd6939SJiyong Park #define SMC_PCI_FEATURES U(0x84000131) 15*54fd6939SJiyong Park #define SMC_PCI_READ U(0x84000132) 16*54fd6939SJiyong Park #define SMC_PCI_WRITE U(0x84000133) 17*54fd6939SJiyong Park #define SMC_PCI_SEG_INFO U(0x84000134) 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park #define is_pci_fid(_fid) (((_fid) >= SMC_PCI_VERSION) && \ 20*54fd6939SJiyong Park ((_fid) <= SMC_PCI_SEG_INFO)) 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park uint64_t pci_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, 23*54fd6939SJiyong Park u_register_t x3, u_register_t x4, void *cookie, 24*54fd6939SJiyong Park void *handle, u_register_t flags); 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park #define PCI_ADDR_FUN(dev) ((dev) & U(0x7)) 27*54fd6939SJiyong Park #define PCI_ADDR_DEV(dev) (((dev) >> U(3)) & U(0x001F)) 28*54fd6939SJiyong Park #define PCI_ADDR_BUS(dev) (((dev) >> U(8)) & U(0x00FF)) 29*54fd6939SJiyong Park #define PCI_ADDR_SEG(dev) (((dev) >> U(16)) & U(0xFFFF)) 30*54fd6939SJiyong Park #define PCI_OFFSET_MASK U(0xFFF) 31*54fd6939SJiyong Park typedef union { 32*54fd6939SJiyong Park struct { 33*54fd6939SJiyong Park uint16_t minor; 34*54fd6939SJiyong Park uint16_t major; 35*54fd6939SJiyong Park } __packed; 36*54fd6939SJiyong Park uint32_t val; 37*54fd6939SJiyong Park } pcie_version; 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park /* 40*54fd6939SJiyong Park * platforms are responsible for providing implementations of these 41*54fd6939SJiyong Park * three functions in a manner which conforms to the Arm PCI Configuration 42*54fd6939SJiyong Park * Space Access Firmware Interface (DEN0115) and the PCIe specification's 43*54fd6939SJiyong Park * sections on PCI configuration access. See the rpi4_pci_svc.c example. 44*54fd6939SJiyong Park */ 45*54fd6939SJiyong Park uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val); 46*54fd6939SJiyong Park uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val); 47*54fd6939SJiyong Park uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg); 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park /* Return codes for Arm PCI Config Space Access Firmware SMC calls */ 50*54fd6939SJiyong Park #define SMC_PCI_CALL_SUCCESS U(0) 51*54fd6939SJiyong Park #define SMC_PCI_CALL_NOT_SUPPORTED -1 52*54fd6939SJiyong Park #define SMC_PCI_CALL_INVAL_PARAM -2 53*54fd6939SJiyong Park #define SMC_PCI_CALL_NOT_IMPL -3 54*54fd6939SJiyong Park 55*54fd6939SJiyong Park #define SMC_PCI_SZ_8BIT U(1) 56*54fd6939SJiyong Park #define SMC_PCI_SZ_16BIT U(2) 57*54fd6939SJiyong Park #define SMC_PCI_SZ_32BIT U(4) 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park #endif /* PCI_SVC_H */ 60