1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park #ifndef COMMON_DEF_H 7*54fd6939SJiyong Park #define COMMON_DEF_H 8*54fd6939SJiyong Park 9*54fd6939SJiyong Park #include <platform_def.h> 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park #include <common/bl_common.h> 12*54fd6939SJiyong Park #include <lib/utils_def.h> 13*54fd6939SJiyong Park #include <lib/xlat_tables/xlat_tables_defs.h> 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park /****************************************************************************** 16*54fd6939SJiyong Park * Required platform porting definitions that are expected to be common to 17*54fd6939SJiyong Park * all platforms 18*54fd6939SJiyong Park *****************************************************************************/ 19*54fd6939SJiyong Park 20*54fd6939SJiyong Park /* 21*54fd6939SJiyong Park * Platform binary types for linking 22*54fd6939SJiyong Park */ 23*54fd6939SJiyong Park #ifdef __aarch64__ 24*54fd6939SJiyong Park #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 25*54fd6939SJiyong Park #define PLATFORM_LINKER_ARCH aarch64 26*54fd6939SJiyong Park #else 27*54fd6939SJiyong Park #define PLATFORM_LINKER_FORMAT "elf32-littlearm" 28*54fd6939SJiyong Park #define PLATFORM_LINKER_ARCH arm 29*54fd6939SJiyong Park #endif /* __aarch64__ */ 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park /* 32*54fd6939SJiyong Park * Generic platform constants 33*54fd6939SJiyong Park */ 34*54fd6939SJiyong Park #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park #define BL2_IMAGE_DESC { \ 37*54fd6939SJiyong Park .image_id = BL2_IMAGE_ID, \ 38*54fd6939SJiyong Park SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ 39*54fd6939SJiyong Park VERSION_2, image_info_t, 0), \ 40*54fd6939SJiyong Park .image_info.image_base = BL2_BASE, \ 41*54fd6939SJiyong Park .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\ 42*54fd6939SJiyong Park SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ 43*54fd6939SJiyong Park VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ 44*54fd6939SJiyong Park .ep_info.pc = BL2_BASE, \ 45*54fd6939SJiyong Park } 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park /* 48*54fd6939SJiyong Park * The following constants identify the extents of the code & read-only data 49*54fd6939SJiyong Park * regions. These addresses are used by the MMU setup code and therefore they 50*54fd6939SJiyong Park * must be page-aligned. 51*54fd6939SJiyong Park * 52*54fd6939SJiyong Park * When the code and read-only data are mapped as a single atomic section 53*54fd6939SJiyong Park * (i.e. when SEPARATE_CODE_AND_RODATA=0) then we treat the whole section as 54*54fd6939SJiyong Park * code by specifying the read-only data section as empty. 55*54fd6939SJiyong Park * 56*54fd6939SJiyong Park * BL1 is different than the other images in the sense that its read-write data 57*54fd6939SJiyong Park * originally lives in Trusted ROM and needs to be relocated in Trusted SRAM at 58*54fd6939SJiyong Park * run-time. Therefore, the read-write data in ROM can be mapped with the same 59*54fd6939SJiyong Park * memory attributes as the read-only data region. For this reason, BL1 uses 60*54fd6939SJiyong Park * different macros. 61*54fd6939SJiyong Park * 62*54fd6939SJiyong Park * Note that BL1_ROM_END is not necessarily aligned on a page boundary as it 63*54fd6939SJiyong Park * just points to the end of BL1's actual content in Trusted ROM. Therefore it 64*54fd6939SJiyong Park * needs to be rounded up to the next page size in order to map the whole last 65*54fd6939SJiyong Park * page of it with the right memory attributes. 66*54fd6939SJiyong Park */ 67*54fd6939SJiyong Park #if SEPARATE_CODE_AND_RODATA 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park #define BL1_CODE_END BL_CODE_END 70*54fd6939SJiyong Park #define BL1_RO_DATA_BASE BL_RO_DATA_BASE 71*54fd6939SJiyong Park #define BL1_RO_DATA_END round_up(BL1_ROM_END, PAGE_SIZE) 72*54fd6939SJiyong Park #if BL2_IN_XIP_MEM 73*54fd6939SJiyong Park #define BL2_CODE_END BL_CODE_END 74*54fd6939SJiyong Park #define BL2_RO_DATA_BASE BL_RO_DATA_BASE 75*54fd6939SJiyong Park #define BL2_RO_DATA_END round_up(BL2_ROM_END, PAGE_SIZE) 76*54fd6939SJiyong Park #endif /* BL2_IN_XIP_MEM */ 77*54fd6939SJiyong Park #else 78*54fd6939SJiyong Park #define BL_RO_DATA_BASE UL(0) 79*54fd6939SJiyong Park #define BL_RO_DATA_END UL(0) 80*54fd6939SJiyong Park #define BL1_CODE_END round_up(BL1_ROM_END, PAGE_SIZE) 81*54fd6939SJiyong Park #if BL2_IN_XIP_MEM 82*54fd6939SJiyong Park #define BL2_RO_DATA_BASE UL(0) 83*54fd6939SJiyong Park #define BL2_RO_DATA_END UL(0) 84*54fd6939SJiyong Park #define BL2_CODE_END round_up(BL2_ROM_END, PAGE_SIZE) 85*54fd6939SJiyong Park #endif /* BL2_IN_XIP_MEM */ 86*54fd6939SJiyong Park #endif /* SEPARATE_CODE_AND_RODATA */ 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park #endif /* COMMON_DEF_H */ 89