1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2020, Arm Limited. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef RAINIER_H 8*54fd6939SJiyong Park #define RAINIER_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <lib/utils_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* RAINIER MIDR for revision 0 */ 13*54fd6939SJiyong Park #define RAINIER_MIDR U(0x3f0f4120) 14*54fd6939SJiyong Park 15*54fd6939SJiyong Park /* Exception Syndrome register EC code for IC Trap */ 16*54fd6939SJiyong Park #define RAINIER_EC_IC_TRAP U(0x1f) 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park /******************************************************************************* 19*54fd6939SJiyong Park * CPU Power Control register specific definitions. 20*54fd6939SJiyong Park ******************************************************************************/ 21*54fd6939SJiyong Park #define RAINIER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park /* Definitions of register field mask in RAINIER_CPUPWRCTLR_EL1 */ 24*54fd6939SJiyong Park #define RAINIER_CORE_PWRDN_EN_MASK U(0x1) 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park #define RAINIER_ACTLR_AMEN_BIT (U(1) << 4) 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park #define RAINIER_AMU_NR_COUNTERS U(5) 29*54fd6939SJiyong Park #define RAINIER_AMU_GROUP0_MASK U(0x1f) 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park /******************************************************************************* 32*54fd6939SJiyong Park * CPU Extended Control register specific definitions. 33*54fd6939SJiyong Park ******************************************************************************/ 34*54fd6939SJiyong Park #define RAINIER_CPUECTLR_EL1 S3_0_C15_C1_4 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24) 37*54fd6939SJiyong Park #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) 38*54fd6939SJiyong Park 39*54fd6939SJiyong Park /******************************************************************************* 40*54fd6939SJiyong Park * CPU Auxiliary Control register specific definitions. 41*54fd6939SJiyong Park ******************************************************************************/ 42*54fd6939SJiyong Park #define RAINIER_CPUACTLR_EL1 S3_0_C15_C1_0 43*54fd6939SJiyong Park 44*54fd6939SJiyong Park #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6) 45*54fd6939SJiyong Park #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13) 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park #define RAINIER_CPUACTLR2_EL1 S3_0_C15_C1_1 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0) 50*54fd6939SJiyong Park #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) 51*54fd6939SJiyong Park #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11) 52*54fd6939SJiyong Park #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15) 53*54fd6939SJiyong Park #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16) 54*54fd6939SJiyong Park #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59) 55*54fd6939SJiyong Park 56*54fd6939SJiyong Park #define RAINIER_CPUACTLR3_EL1 S3_0_C15_C1_2 57*54fd6939SJiyong Park 58*54fd6939SJiyong Park #define RAINIER_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10) 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park /* Instruction patching registers */ 61*54fd6939SJiyong Park #define CPUPSELR_EL3 S3_6_C15_C8_0 62*54fd6939SJiyong Park #define CPUPCR_EL3 S3_6_C15_C8_1 63*54fd6939SJiyong Park #define CPUPOR_EL3 S3_6_C15_C8_2 64*54fd6939SJiyong Park #define CPUPMR_EL3 S3_6_C15_C8_3 65*54fd6939SJiyong Park 66*54fd6939SJiyong Park #endif /* RAINIER_H */ 67