1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef DENVER_H 8*54fd6939SJiyong Park #define DENVER_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park /* MIDR values for Denver */ 11*54fd6939SJiyong Park #define DENVER_MIDR_PN0 U(0x4E0F0000) 12*54fd6939SJiyong Park #define DENVER_MIDR_PN1 U(0x4E0F0010) 13*54fd6939SJiyong Park #define DENVER_MIDR_PN2 U(0x4E0F0020) 14*54fd6939SJiyong Park #define DENVER_MIDR_PN3 U(0x4E0F0030) 15*54fd6939SJiyong Park #define DENVER_MIDR_PN4 U(0x4E0F0040) 16*54fd6939SJiyong Park #define DENVER_MIDR_PN5 U(0x4E0F0050) 17*54fd6939SJiyong Park #define DENVER_MIDR_PN6 U(0x4E0F0060) 18*54fd6939SJiyong Park #define DENVER_MIDR_PN7 U(0x4E0F0070) 19*54fd6939SJiyong Park #define DENVER_MIDR_PN8 U(0x4E0F0080) 20*54fd6939SJiyong Park #define DENVER_MIDR_PN9 U(0x4E0F0090) 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park /* Implementer code in the MIDR register */ 23*54fd6939SJiyong Park #define DENVER_IMPL U(0x4E) 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park /* CPU state ids - implementation defined */ 26*54fd6939SJiyong Park #define DENVER_CPU_STATE_POWER_DOWN U(0x3) 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park /* Speculative store buffering */ 29*54fd6939SJiyong Park #define DENVER_CPU_DIS_SSB_EL3 (U(1) << 11) 30*54fd6939SJiyong Park #define DENVER_PN4_CPU_DIS_SSB_EL3 (U(1) << 18) 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park /* Speculative memory disambiguation */ 33*54fd6939SJiyong Park #define DENVER_CPU_DIS_MD_EL3 (U(1) << 9) 34*54fd6939SJiyong Park #define DENVER_PN4_CPU_DIS_MD_EL3 (U(1) << 17) 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park /* Core power management states */ 37*54fd6939SJiyong Park #define DENVER_CPU_PMSTATE_C1 U(0x1) 38*54fd6939SJiyong Park #define DENVER_CPU_PMSTATE_C6 U(0x6) 39*54fd6939SJiyong Park #define DENVER_CPU_PMSTATE_C7 U(0x7) 40*54fd6939SJiyong Park #define DENVER_CPU_PMSTATE_MASK U(0xF) 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park /* ACTRL_ELx bits to enable dual execution*/ 43*54fd6939SJiyong Park #define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9) 44*54fd6939SJiyong Park #define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9) 45*54fd6939SJiyong Park #define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4) 46*54fd6939SJiyong Park 47*54fd6939SJiyong Park #ifndef __ASSEMBLER__ 48*54fd6939SJiyong Park 49*54fd6939SJiyong Park /* Disable Dynamic Code Optimisation */ 50*54fd6939SJiyong Park void denver_disable_dco(void); 51*54fd6939SJiyong Park 52*54fd6939SJiyong Park #endif /* __ASSEMBLER__ */ 53*54fd6939SJiyong Park 54*54fd6939SJiyong Park #endif /* DENVER_H */ 55