1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef CPUAMU_H 8*54fd6939SJiyong Park #define CPUAMU_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park /******************************************************************************* 11*54fd6939SJiyong Park * CPU Activity Monitor Unit register specific definitions. 12*54fd6939SJiyong Park ******************************************************************************/ 13*54fd6939SJiyong Park #define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7 14*54fd6939SJiyong Park #define CPUAMCNTENSET_EL0 S3_3_C15_C9_6 15*54fd6939SJiyong Park #define CPUAMCFGR_EL0 S3_3_C15_C10_6 16*54fd6939SJiyong Park #define CPUAMUSERENR_EL0 S3_3_C15_C10_7 17*54fd6939SJiyong Park 18*54fd6939SJiyong Park /* Activity Monitor Event Counter Registers */ 19*54fd6939SJiyong Park #define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0 20*54fd6939SJiyong Park #define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1 21*54fd6939SJiyong Park #define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2 22*54fd6939SJiyong Park #define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3 23*54fd6939SJiyong Park #define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park /* Activity Monitor Event Type Registers */ 26*54fd6939SJiyong Park #define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0 27*54fd6939SJiyong Park #define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1 28*54fd6939SJiyong Park #define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2 29*54fd6939SJiyong Park #define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3 30*54fd6939SJiyong Park #define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park #ifndef __ASSEMBLER__ 33*54fd6939SJiyong Park #include <stdint.h> 34*54fd6939SJiyong Park 35*54fd6939SJiyong Park uint64_t cpuamu_cnt_read(unsigned int idx); 36*54fd6939SJiyong Park void cpuamu_cnt_write(unsigned int idx, uint64_t val); 37*54fd6939SJiyong Park unsigned int cpuamu_read_cpuamcntenset_el0(void); 38*54fd6939SJiyong Park unsigned int cpuamu_read_cpuamcntenclr_el0(void); 39*54fd6939SJiyong Park void cpuamu_write_cpuamcntenset_el0(unsigned int mask); 40*54fd6939SJiyong Park void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park int midr_match(unsigned int cpu_midr); 43*54fd6939SJiyong Park void cpuamu_context_save(unsigned int nr_counters); 44*54fd6939SJiyong Park void cpuamu_context_restore(unsigned int nr_counters); 45*54fd6939SJiyong Park 46*54fd6939SJiyong Park #endif /* __ASSEMBLER__ */ 47*54fd6939SJiyong Park 48*54fd6939SJiyong Park #endif /* CPUAMU_H */ 49