1*54fd6939SJiyong Park /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2*54fd6939SJiyong Park /* 3*54fd6939SJiyong Park * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 4*54fd6939SJiyong Park * Author: Gabriel Fernandez <[email protected]> for STMicroelectronics. 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef _DT_BINDINGS_STM32MP1_RESET_H_ 8*54fd6939SJiyong Park #define _DT_BINDINGS_STM32MP1_RESET_H_ 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #define LTDC_R 3072 11*54fd6939SJiyong Park #define DSI_R 3076 12*54fd6939SJiyong Park #define DDRPERFM_R 3080 13*54fd6939SJiyong Park #define USBPHY_R 3088 14*54fd6939SJiyong Park #define SPI6_R 3136 15*54fd6939SJiyong Park #define I2C4_R 3138 16*54fd6939SJiyong Park #define I2C6_R 3139 17*54fd6939SJiyong Park #define USART1_R 3140 18*54fd6939SJiyong Park #define STGEN_R 3156 19*54fd6939SJiyong Park #define GPIOZ_R 3200 20*54fd6939SJiyong Park #define CRYP1_R 3204 21*54fd6939SJiyong Park #define HASH1_R 3205 22*54fd6939SJiyong Park #define RNG1_R 3206 23*54fd6939SJiyong Park #define AXIM_R 3216 24*54fd6939SJiyong Park #define GPU_R 3269 25*54fd6939SJiyong Park #define ETHMAC_R 3274 26*54fd6939SJiyong Park #define FMC_R 3276 27*54fd6939SJiyong Park #define QSPI_R 3278 28*54fd6939SJiyong Park #define SDMMC1_R 3280 29*54fd6939SJiyong Park #define SDMMC2_R 3281 30*54fd6939SJiyong Park #define CRC1_R 3284 31*54fd6939SJiyong Park #define USBH_R 3288 32*54fd6939SJiyong Park #define MDMA_R 3328 33*54fd6939SJiyong Park #define MCU_R 8225 34*54fd6939SJiyong Park #define TIM2_R 19456 35*54fd6939SJiyong Park #define TIM3_R 19457 36*54fd6939SJiyong Park #define TIM4_R 19458 37*54fd6939SJiyong Park #define TIM5_R 19459 38*54fd6939SJiyong Park #define TIM6_R 19460 39*54fd6939SJiyong Park #define TIM7_R 19461 40*54fd6939SJiyong Park #define TIM12_R 16462 41*54fd6939SJiyong Park #define TIM13_R 16463 42*54fd6939SJiyong Park #define TIM14_R 16464 43*54fd6939SJiyong Park #define LPTIM1_R 19465 44*54fd6939SJiyong Park #define SPI2_R 19467 45*54fd6939SJiyong Park #define SPI3_R 19468 46*54fd6939SJiyong Park #define USART2_R 19470 47*54fd6939SJiyong Park #define USART3_R 19471 48*54fd6939SJiyong Park #define UART4_R 19472 49*54fd6939SJiyong Park #define UART5_R 19473 50*54fd6939SJiyong Park #define UART7_R 19474 51*54fd6939SJiyong Park #define UART8_R 19475 52*54fd6939SJiyong Park #define I2C1_R 19477 53*54fd6939SJiyong Park #define I2C2_R 19478 54*54fd6939SJiyong Park #define I2C3_R 19479 55*54fd6939SJiyong Park #define I2C5_R 19480 56*54fd6939SJiyong Park #define SPDIF_R 19482 57*54fd6939SJiyong Park #define CEC_R 19483 58*54fd6939SJiyong Park #define DAC12_R 19485 59*54fd6939SJiyong Park #define MDIO_R 19847 60*54fd6939SJiyong Park #define TIM1_R 19520 61*54fd6939SJiyong Park #define TIM8_R 19521 62*54fd6939SJiyong Park #define TIM15_R 19522 63*54fd6939SJiyong Park #define TIM16_R 19523 64*54fd6939SJiyong Park #define TIM17_R 19524 65*54fd6939SJiyong Park #define SPI1_R 19528 66*54fd6939SJiyong Park #define SPI4_R 19529 67*54fd6939SJiyong Park #define SPI5_R 19530 68*54fd6939SJiyong Park #define USART6_R 19533 69*54fd6939SJiyong Park #define SAI1_R 19536 70*54fd6939SJiyong Park #define SAI2_R 19537 71*54fd6939SJiyong Park #define SAI3_R 19538 72*54fd6939SJiyong Park #define DFSDM_R 19540 73*54fd6939SJiyong Park #define FDCAN_R 19544 74*54fd6939SJiyong Park #define LPTIM2_R 19584 75*54fd6939SJiyong Park #define LPTIM3_R 19585 76*54fd6939SJiyong Park #define LPTIM4_R 19586 77*54fd6939SJiyong Park #define LPTIM5_R 19587 78*54fd6939SJiyong Park #define SAI4_R 19592 79*54fd6939SJiyong Park #define SYSCFG_R 19595 80*54fd6939SJiyong Park #define VREF_R 19597 81*54fd6939SJiyong Park #define TMPSENS_R 19600 82*54fd6939SJiyong Park #define PMBCTRL_R 19601 83*54fd6939SJiyong Park #define DMA1_R 19648 84*54fd6939SJiyong Park #define DMA2_R 19649 85*54fd6939SJiyong Park #define DMAMUX_R 19650 86*54fd6939SJiyong Park #define ADC12_R 19653 87*54fd6939SJiyong Park #define USBO_R 19656 88*54fd6939SJiyong Park #define SDMMC3_R 19664 89*54fd6939SJiyong Park #define CAMITF_R 19712 90*54fd6939SJiyong Park #define CRYP2_R 19716 91*54fd6939SJiyong Park #define HASH2_R 19717 92*54fd6939SJiyong Park #define RNG2_R 19718 93*54fd6939SJiyong Park #define CRC2_R 19719 94*54fd6939SJiyong Park #define HSEM_R 19723 95*54fd6939SJiyong Park #define MBOX_R 19724 96*54fd6939SJiyong Park #define GPIOA_R 19776 97*54fd6939SJiyong Park #define GPIOB_R 19777 98*54fd6939SJiyong Park #define GPIOC_R 19778 99*54fd6939SJiyong Park #define GPIOD_R 19779 100*54fd6939SJiyong Park #define GPIOE_R 19780 101*54fd6939SJiyong Park #define GPIOF_R 19781 102*54fd6939SJiyong Park #define GPIOG_R 19782 103*54fd6939SJiyong Park #define GPIOH_R 19783 104*54fd6939SJiyong Park #define GPIOI_R 19784 105*54fd6939SJiyong Park #define GPIOJ_R 19785 106*54fd6939SJiyong Park #define GPIOK_R 19786 107*54fd6939SJiyong Park 108*54fd6939SJiyong Park /* SCMI reset domain identifiers */ 109*54fd6939SJiyong Park #define RST_SCMI0_SPI6 0 110*54fd6939SJiyong Park #define RST_SCMI0_I2C4 1 111*54fd6939SJiyong Park #define RST_SCMI0_I2C6 2 112*54fd6939SJiyong Park #define RST_SCMI0_USART1 3 113*54fd6939SJiyong Park #define RST_SCMI0_STGEN 4 114*54fd6939SJiyong Park #define RST_SCMI0_GPIOZ 5 115*54fd6939SJiyong Park #define RST_SCMI0_CRYP1 6 116*54fd6939SJiyong Park #define RST_SCMI0_HASH1 7 117*54fd6939SJiyong Park #define RST_SCMI0_RNG1 8 118*54fd6939SJiyong Park #define RST_SCMI0_MDMA 9 119*54fd6939SJiyong Park #define RST_SCMI0_MCU 10 120*54fd6939SJiyong Park 121*54fd6939SJiyong Park #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ 122