1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef STM32MP1_PWR_H 8*54fd6939SJiyong Park #define STM32MP1_PWR_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <lib/utils_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park #define PWR_CR1 U(0x00) 13*54fd6939SJiyong Park #define PWR_CR2 U(0x08) 14*54fd6939SJiyong Park #define PWR_CR3 U(0x0C) 15*54fd6939SJiyong Park #define PWR_MPUCR U(0x10) 16*54fd6939SJiyong Park #define PWR_WKUPCR U(0x20) 17*54fd6939SJiyong Park #define PWR_MPUWKUPENR U(0x28) 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park #define PWR_CR1_LPDS BIT(0) 20*54fd6939SJiyong Park #define PWR_CR1_LPCFG BIT(1) 21*54fd6939SJiyong Park #define PWR_CR1_LVDS BIT(2) 22*54fd6939SJiyong Park #define PWR_CR1_DBP BIT(8) 23*54fd6939SJiyong Park 24*54fd6939SJiyong Park #define PWR_CR3_DDRSREN BIT(10) 25*54fd6939SJiyong Park #define PWR_CR3_DDRSRDIS BIT(11) 26*54fd6939SJiyong Park #define PWR_CR3_DDRRETEN BIT(12) 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park #define PWR_MPUCR_PDDS BIT(0) 29*54fd6939SJiyong Park #define PWR_MPUCR_CSTDBYDIS BIT(3) 30*54fd6939SJiyong Park #define PWR_MPUCR_CSSF BIT(9) 31*54fd6939SJiyong Park 32*54fd6939SJiyong Park #endif /* STM32MP1_PWR_H */ 33