1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef DRIVERS_SPI_NOR_H 8*54fd6939SJiyong Park #define DRIVERS_SPI_NOR_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <drivers/spi_mem.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /* OPCODE */ 13*54fd6939SJiyong Park #define SPI_NOR_OP_WREN 0x06U /* Write enable */ 14*54fd6939SJiyong Park #define SPI_NOR_OP_WRSR 0x01U /* Write status register 1 byte */ 15*54fd6939SJiyong Park #define SPI_NOR_OP_READ_ID 0x9FU /* Read JEDEC ID */ 16*54fd6939SJiyong Park #define SPI_NOR_OP_READ_CR 0x35U /* Read configuration register */ 17*54fd6939SJiyong Park #define SPI_NOR_OP_READ_SR 0x05U /* Read status register */ 18*54fd6939SJiyong Park #define SPI_NOR_OP_READ_FSR 0x70U /* Read flag status register */ 19*54fd6939SJiyong Park #define SPINOR_OP_RDEAR 0xC8U /* Read Extended Address Register */ 20*54fd6939SJiyong Park #define SPINOR_OP_WREAR 0xC5U /* Write Extended Address Register */ 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park /* Used for Spansion flashes only. */ 23*54fd6939SJiyong Park #define SPINOR_OP_BRWR 0x17U /* Bank register write */ 24*54fd6939SJiyong Park #define SPINOR_OP_BRRD 0x16U /* Bank register read */ 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park #define SPI_NOR_OP_READ 0x03U /* Read data bytes (low frequency) */ 27*54fd6939SJiyong Park #define SPI_NOR_OP_READ_FAST 0x0BU /* Read data bytes (high frequency) */ 28*54fd6939SJiyong Park #define SPI_NOR_OP_READ_1_1_2 0x3BU /* Read data bytes (Dual Output SPI) */ 29*54fd6939SJiyong Park #define SPI_NOR_OP_READ_1_2_2 0xBBU /* Read data bytes (Dual I/O SPI) */ 30*54fd6939SJiyong Park #define SPI_NOR_OP_READ_1_1_4 0x6BU /* Read data bytes (Quad Output SPI) */ 31*54fd6939SJiyong Park #define SPI_NOR_OP_READ_1_4_4 0xEBU /* Read data bytes (Quad I/O SPI) */ 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park /* Flags for NOR specific configuration */ 34*54fd6939SJiyong Park #define SPI_NOR_USE_FSR BIT(0) 35*54fd6939SJiyong Park #define SPI_NOR_USE_BANK BIT(1) 36*54fd6939SJiyong Park 37*54fd6939SJiyong Park struct nor_device { 38*54fd6939SJiyong Park struct spi_mem_op read_op; 39*54fd6939SJiyong Park uint32_t size; 40*54fd6939SJiyong Park uint32_t flags; 41*54fd6939SJiyong Park uint8_t selected_bank; 42*54fd6939SJiyong Park uint8_t bank_write_cmd; 43*54fd6939SJiyong Park uint8_t bank_read_cmd; 44*54fd6939SJiyong Park }; 45*54fd6939SJiyong Park 46*54fd6939SJiyong Park int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length, 47*54fd6939SJiyong Park size_t *length_read); 48*54fd6939SJiyong Park int spi_nor_init(unsigned long long *device_size, unsigned int *erase_size); 49*54fd6939SJiyong Park 50*54fd6939SJiyong Park /* 51*54fd6939SJiyong Park * Platform can implement this to override default NOR instance configuration. 52*54fd6939SJiyong Park * 53*54fd6939SJiyong Park * @device: target NOR instance. 54*54fd6939SJiyong Park * Return 0 on success, negative value otherwise. 55*54fd6939SJiyong Park */ 56*54fd6939SJiyong Park int plat_get_nor_data(struct nor_device *device); 57*54fd6939SJiyong Park 58*54fd6939SJiyong Park #endif /* DRIVERS_SPI_NOR_H */ 59