xref: /aosp_15_r20/external/arm-trusted-firmware/include/drivers/nxp/ddr/ddr.h (revision 54fd6939e177f8ff529b10183254802c76df6d08)
1*54fd6939SJiyong Park /*
2*54fd6939SJiyong Park  * Copyright 2021 NXP
3*54fd6939SJiyong Park  *
4*54fd6939SJiyong Park  * SPDX-License-Identifier: BSD-3-Clause
5*54fd6939SJiyong Park  *
6*54fd6939SJiyong Park  */
7*54fd6939SJiyong Park 
8*54fd6939SJiyong Park #ifndef DDR_H
9*54fd6939SJiyong Park #define DDR_H
10*54fd6939SJiyong Park 
11*54fd6939SJiyong Park #include "ddr_io.h"
12*54fd6939SJiyong Park #include "dimm.h"
13*54fd6939SJiyong Park #include "immap.h"
14*54fd6939SJiyong Park 
15*54fd6939SJiyong Park #ifndef DDRC_NUM_CS
16*54fd6939SJiyong Park #define DDRC_NUM_CS 4
17*54fd6939SJiyong Park #endif
18*54fd6939SJiyong Park 
19*54fd6939SJiyong Park /*
20*54fd6939SJiyong Park  * This is irrespective of what is the number of DDR controller,
21*54fd6939SJiyong Park  * number of DIMM used. This is set to maximum
22*54fd6939SJiyong Park  * Max controllers = 2
23*54fd6939SJiyong Park  * Max num of DIMM per controlle = 2
24*54fd6939SJiyong Park  * MAX NUM CS = 4
25*54fd6939SJiyong Park  * Not to be changed.
26*54fd6939SJiyong Park  */
27*54fd6939SJiyong Park #define MAX_DDRC_NUM	2
28*54fd6939SJiyong Park #define MAX_DIMM_NUM	2
29*54fd6939SJiyong Park #define MAX_CS_NUM	4
30*54fd6939SJiyong Park 
31*54fd6939SJiyong Park #include "opts.h"
32*54fd6939SJiyong Park #include "regs.h"
33*54fd6939SJiyong Park #include "utility.h"
34*54fd6939SJiyong Park 
35*54fd6939SJiyong Park #ifdef DDR_DEBUG
36*54fd6939SJiyong Park #define debug(...) INFO(__VA_ARGS__)
37*54fd6939SJiyong Park #else
38*54fd6939SJiyong Park #define debug(...) VERBOSE(__VA_ARGS__)
39*54fd6939SJiyong Park #endif
40*54fd6939SJiyong Park 
41*54fd6939SJiyong Park #ifndef DDRC_NUM_DIMM
42*54fd6939SJiyong Park #define DDRC_NUM_DIMM 1
43*54fd6939SJiyong Park #endif
44*54fd6939SJiyong Park 
45*54fd6939SJiyong Park #define CONFIG_CS_PER_SLOT \
46*54fd6939SJiyong Park 	(DDRC_NUM_CS / DDRC_NUM_DIMM)
47*54fd6939SJiyong Park 
48*54fd6939SJiyong Park /* Record of register values computed */
49*54fd6939SJiyong Park struct ddr_cfg_regs {
50*54fd6939SJiyong Park 	struct {
51*54fd6939SJiyong Park 		unsigned int bnds;
52*54fd6939SJiyong Park 		unsigned int config;
53*54fd6939SJiyong Park 		unsigned int config_2;
54*54fd6939SJiyong Park 	} cs[MAX_CS_NUM];
55*54fd6939SJiyong Park 	unsigned int dec[10];
56*54fd6939SJiyong Park 	unsigned int timing_cfg[10];
57*54fd6939SJiyong Park 	unsigned int sdram_cfg[3];
58*54fd6939SJiyong Park 	unsigned int sdram_mode[16];
59*54fd6939SJiyong Park 	unsigned int md_cntl;
60*54fd6939SJiyong Park 	unsigned int interval;
61*54fd6939SJiyong Park 	unsigned int data_init;
62*54fd6939SJiyong Park 	unsigned int clk_cntl;
63*54fd6939SJiyong Park 	unsigned int init_addr;
64*54fd6939SJiyong Park 	unsigned int init_ext_addr;
65*54fd6939SJiyong Park 	unsigned int zq_cntl;
66*54fd6939SJiyong Park 	unsigned int wrlvl_cntl[3];
67*54fd6939SJiyong Park 	unsigned int ddr_sr_cntr;
68*54fd6939SJiyong Park 	unsigned int sdram_rcw[6];
69*54fd6939SJiyong Park 	unsigned int dq_map[4];
70*54fd6939SJiyong Park 	unsigned int eor;
71*54fd6939SJiyong Park 	unsigned int cdr[2];
72*54fd6939SJiyong Park 	unsigned int err_disable;
73*54fd6939SJiyong Park 	unsigned int err_int_en;
74*54fd6939SJiyong Park 	unsigned int tx_cfg[4];
75*54fd6939SJiyong Park 	unsigned int debug[64];
76*54fd6939SJiyong Park };
77*54fd6939SJiyong Park 
78*54fd6939SJiyong Park struct ddr_conf {
79*54fd6939SJiyong Park 	int dimm_in_use[MAX_DIMM_NUM];
80*54fd6939SJiyong Park 	int cs_in_use;	/* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */
81*54fd6939SJiyong Park 	int cs_on_dimm[MAX_DIMM_NUM];	/* bitmask */
82*54fd6939SJiyong Park 	unsigned long long cs_base_addr[MAX_CS_NUM];
83*54fd6939SJiyong Park 	unsigned long long cs_size[MAX_CS_NUM];
84*54fd6939SJiyong Park 	unsigned long long base_addr;
85*54fd6939SJiyong Park 	unsigned long long total_mem;
86*54fd6939SJiyong Park };
87*54fd6939SJiyong Park 
88*54fd6939SJiyong Park struct ddr_info {
89*54fd6939SJiyong Park 	unsigned long clk;
90*54fd6939SJiyong Park 	unsigned long long mem_base;
91*54fd6939SJiyong Park 	unsigned int num_ctlrs;
92*54fd6939SJiyong Park 	unsigned int dimm_on_ctlr;
93*54fd6939SJiyong Park 	struct dimm_params dimm;
94*54fd6939SJiyong Park 	struct memctl_opt opt;
95*54fd6939SJiyong Park 	struct ddr_conf conf;
96*54fd6939SJiyong Park 	struct ddr_cfg_regs ddr_reg;
97*54fd6939SJiyong Park 	struct ccsr_ddr *ddr[MAX_DDRC_NUM];
98*54fd6939SJiyong Park 	uint16_t *phy[MAX_DDRC_NUM];
99*54fd6939SJiyong Park 	int *spd_addr;
100*54fd6939SJiyong Park 	unsigned int ip_rev;
101*54fd6939SJiyong Park 	uintptr_t phy_gen2_fw_img_buf;
102*54fd6939SJiyong Park 	void *img_loadr;
103*54fd6939SJiyong Park 	int warm_boot_flag;
104*54fd6939SJiyong Park };
105*54fd6939SJiyong Park 
106*54fd6939SJiyong Park struct rc_timing {
107*54fd6939SJiyong Park 	unsigned int speed_bin;
108*54fd6939SJiyong Park 	unsigned int clk_adj;
109*54fd6939SJiyong Park 	unsigned int wrlvl;
110*54fd6939SJiyong Park };
111*54fd6939SJiyong Park 
112*54fd6939SJiyong Park struct board_timing {
113*54fd6939SJiyong Park 	unsigned int rc;
114*54fd6939SJiyong Park 	struct rc_timing const *p;
115*54fd6939SJiyong Park 	unsigned int add1;
116*54fd6939SJiyong Park 	unsigned int add2;
117*54fd6939SJiyong Park };
118*54fd6939SJiyong Park 
119*54fd6939SJiyong Park enum warm_boot {
120*54fd6939SJiyong Park 	DDR_COLD_BOOT = 0,
121*54fd6939SJiyong Park 	DDR_WARM_BOOT = 1,
122*54fd6939SJiyong Park 	DDR_WRM_BOOT_NT_SUPPORTED = -1,
123*54fd6939SJiyong Park };
124*54fd6939SJiyong Park 
125*54fd6939SJiyong Park int disable_unused_ddrc(struct ddr_info *priv, int mask,
126*54fd6939SJiyong Park 			uintptr_t nxp_ccn_hn_f0_addr);
127*54fd6939SJiyong Park int ddr_board_options(struct ddr_info *priv);
128*54fd6939SJiyong Park int compute_ddrc(const unsigned long clk,
129*54fd6939SJiyong Park 		 const struct memctl_opt *popts,
130*54fd6939SJiyong Park 		 const struct ddr_conf *conf,
131*54fd6939SJiyong Park 		 struct ddr_cfg_regs *ddr,
132*54fd6939SJiyong Park 		 const struct dimm_params *dimm_params,
133*54fd6939SJiyong Park 		 const unsigned int ip_rev);
134*54fd6939SJiyong Park int compute_ddr_phy(struct ddr_info *priv);
135*54fd6939SJiyong Park int ddrc_set_regs(const unsigned long clk,
136*54fd6939SJiyong Park 		  const struct ddr_cfg_regs *regs,
137*54fd6939SJiyong Park 		  const struct ccsr_ddr *ddr,
138*54fd6939SJiyong Park 		  int twopass);
139*54fd6939SJiyong Park int cal_board_params(struct ddr_info *priv,
140*54fd6939SJiyong Park 		     const struct board_timing *dimm,
141*54fd6939SJiyong Park 		     int len);
142*54fd6939SJiyong Park /* return bit mask of used DIMM(s) */
143*54fd6939SJiyong Park int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf);
144*54fd6939SJiyong Park long long dram_init(struct ddr_info *priv
145*54fd6939SJiyong Park #if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
146*54fd6939SJiyong Park 		    , uintptr_t nxp_ccn_hn_f0_addr
147*54fd6939SJiyong Park #endif
148*54fd6939SJiyong Park 		);
149*54fd6939SJiyong Park long long board_static_ddr(struct ddr_info *info);
150*54fd6939SJiyong Park 
151*54fd6939SJiyong Park #endif	/* DDR_H */
152