1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright 2018-2021 NXP 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park * 6*54fd6939SJiyong Park */ 7*54fd6939SJiyong Park 8*54fd6939SJiyong Park #ifndef DCFG_H 9*54fd6939SJiyong Park #define DCFG_H 10*54fd6939SJiyong Park 11*54fd6939SJiyong Park #include <endian.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park #if defined(CONFIG_CHASSIS_2) 14*54fd6939SJiyong Park #include <dcfg_lsch2.h> 15*54fd6939SJiyong Park #elif defined(CONFIG_CHASSIS_3_2) 16*54fd6939SJiyong Park #include <dcfg_lsch3.h> 17*54fd6939SJiyong Park #endif 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park #ifdef NXP_GUR_BE 20*54fd6939SJiyong Park #define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 21*54fd6939SJiyong Park #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 22*54fd6939SJiyong Park #elif defined(NXP_GUR_LE) 23*54fd6939SJiyong Park #define gur_in32(a) mmio_read_32((uintptr_t)(a)) 24*54fd6939SJiyong Park #define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v) 25*54fd6939SJiyong Park #else 26*54fd6939SJiyong Park #error Please define CCSR GUR register endianness 27*54fd6939SJiyong Park #endif 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park typedef struct { 30*54fd6939SJiyong Park union { 31*54fd6939SJiyong Park uint32_t val; 32*54fd6939SJiyong Park struct { 33*54fd6939SJiyong Park uint32_t min_ver:4; 34*54fd6939SJiyong Park uint32_t maj_ver:4; 35*54fd6939SJiyong Park #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 36*54fd6939SJiyong Park uint32_t personality:6; 37*54fd6939SJiyong Park uint32_t rsv1:2; 38*54fd6939SJiyong Park #elif defined(CONFIG_CHASSIS_2) 39*54fd6939SJiyong Park uint32_t personality:8; 40*54fd6939SJiyong Park 41*54fd6939SJiyong Park #endif 42*54fd6939SJiyong Park #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 43*54fd6939SJiyong Park uint32_t dev_id:6; 44*54fd6939SJiyong Park uint32_t rsv2:2; 45*54fd6939SJiyong Park uint32_t family:4; 46*54fd6939SJiyong Park #elif defined(CONFIG_CHASSIS_2) 47*54fd6939SJiyong Park uint32_t dev_id:12; 48*54fd6939SJiyong Park #endif 49*54fd6939SJiyong Park uint32_t mfr_id; 50*54fd6939SJiyong Park } __packed bf; 51*54fd6939SJiyong Park struct { 52*54fd6939SJiyong Park uint32_t maj_min:8; 53*54fd6939SJiyong Park uint32_t version; /* SoC version without major and minor info */ 54*54fd6939SJiyong Park } __packed bf_ver; 55*54fd6939SJiyong Park } __packed svr_reg; 56*54fd6939SJiyong Park bool sec_enabled; 57*54fd6939SJiyong Park bool is_populated; 58*54fd6939SJiyong Park } soc_info_t; 59*54fd6939SJiyong Park 60*54fd6939SJiyong Park typedef struct { 61*54fd6939SJiyong Park bool is_populated; 62*54fd6939SJiyong Park uint8_t ocram_present; 63*54fd6939SJiyong Park uint8_t ddrc1_present; 64*54fd6939SJiyong Park #if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2) 65*54fd6939SJiyong Park uint8_t ddrc2_present; 66*54fd6939SJiyong Park #endif 67*54fd6939SJiyong Park } devdisr5_info_t; 68*54fd6939SJiyong Park 69*54fd6939SJiyong Park typedef struct { 70*54fd6939SJiyong Park uint32_t porsr1; 71*54fd6939SJiyong Park uintptr_t g_nxp_dcfg_addr; 72*54fd6939SJiyong Park unsigned long nxp_sysclk_freq; 73*54fd6939SJiyong Park unsigned long nxp_ddrclk_freq; 74*54fd6939SJiyong Park unsigned int nxp_plat_clk_divider; 75*54fd6939SJiyong Park } dcfg_init_info_t; 76*54fd6939SJiyong Park 77*54fd6939SJiyong Park 78*54fd6939SJiyong Park struct sysinfo { 79*54fd6939SJiyong Park unsigned long freq_platform; 80*54fd6939SJiyong Park unsigned long freq_ddr_pll0; 81*54fd6939SJiyong Park unsigned long freq_ddr_pll1; 82*54fd6939SJiyong Park }; 83*54fd6939SJiyong Park 84*54fd6939SJiyong Park int get_clocks(struct sysinfo *sys); 85*54fd6939SJiyong Park 86*54fd6939SJiyong Park /* Read the PORSR1 register */ 87*54fd6939SJiyong Park uint32_t read_reg_porsr1(void); 88*54fd6939SJiyong Park 89*54fd6939SJiyong Park /******************************************************************************* 90*54fd6939SJiyong Park * Returns true if secur eboot is enabled on board 91*54fd6939SJiyong Park * mode = 0 (development mode - sb_en = 1) 92*54fd6939SJiyong Park * mode = 1 (production mode - ITS = 1) 93*54fd6939SJiyong Park ******************************************************************************/ 94*54fd6939SJiyong Park bool check_boot_mode_secure(uint32_t *mode); 95*54fd6939SJiyong Park 96*54fd6939SJiyong Park const soc_info_t *get_soc_info(); 97*54fd6939SJiyong Park const devdisr5_info_t *get_devdisr5_info(); 98*54fd6939SJiyong Park 99*54fd6939SJiyong Park void dcfg_init(dcfg_init_info_t *dcfg_init_data); 100*54fd6939SJiyong Park bool is_sec_enabled(void); 101*54fd6939SJiyong Park 102*54fd6939SJiyong Park void error_handler(int error_code); 103*54fd6939SJiyong Park #endif /* DCFG_H */ 104