1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2016 - 2021, Broadcom 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef MDIO_H 8*54fd6939SJiyong Park #define MDIO_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #define CMIC_MIIM_PARAM (PLAT_CMIC_MIIM_BASE + 0x23cU) 11*54fd6939SJiyong Park #define MDIO_PARAM_MIIM_CYCLE 29U 12*54fd6939SJiyong Park #define MDIO_PARAM_INTERNAL_SEL 25U 13*54fd6939SJiyong Park #define MDIO_PARAM_BUSID 22U 14*54fd6939SJiyong Park #define MDIO_PARAM_BUSID_MASK 0x7U 15*54fd6939SJiyong Park #define MDIO_PARAM_C45_SEL 21U 16*54fd6939SJiyong Park #define MDIO_PARAM_PHYID 16U 17*54fd6939SJiyong Park #define MDIO_PARAM_PHYID_MASK 0x1FU 18*54fd6939SJiyong Park #define MDIO_PARAM_DATA 0U 19*54fd6939SJiyong Park #define MDIO_PARAM_DATA_MASK 0xFFFFU 20*54fd6939SJiyong Park #define CMIC_MIIM_READ_DATA (PLAT_CMIC_MIIM_BASE + 0x240U) 21*54fd6939SJiyong Park #define MDIO_READ_DATA_MASK 0xffffU 22*54fd6939SJiyong Park #define CMIC_MIIM_ADDRESS (PLAT_CMIC_MIIM_BASE + 0x244U) 23*54fd6939SJiyong Park #define CMIC_MIIM_CTRL (PLAT_CMIC_MIIM_BASE + 0x248U) 24*54fd6939SJiyong Park #define MDIO_CTRL_WRITE_OP 0x1U 25*54fd6939SJiyong Park #define MDIO_CTRL_READ_OP 0x2U 26*54fd6939SJiyong Park #define CMIC_MIIM_STAT (PLAT_CMIC_MIIM_BASE + 0x24cU) 27*54fd6939SJiyong Park #define MDIO_STAT_DONE 1U 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val); 30*54fd6939SJiyong Park int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg); 31*54fd6939SJiyong Park #endif /* MDIO_H */ 32