1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef SMMU_V3_H 8*54fd6939SJiyong Park #define SMMU_V3_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <stdint.h> 11*54fd6939SJiyong Park #include <lib/utils_def.h> 12*54fd6939SJiyong Park 13*54fd6939SJiyong Park /* SMMUv3 register offsets from device base */ 14*54fd6939SJiyong Park #define SMMU_GBPA U(0x0044) 15*54fd6939SJiyong Park #define SMMU_S_IDR1 U(0x8004) 16*54fd6939SJiyong Park #define SMMU_S_INIT U(0x803c) 17*54fd6939SJiyong Park #define SMMU_S_GBPA U(0x8044) 18*54fd6939SJiyong Park 19*54fd6939SJiyong Park /* SMMU_GBPA register fields */ 20*54fd6939SJiyong Park #define SMMU_GBPA_UPDATE (1UL << 31) 21*54fd6939SJiyong Park #define SMMU_GBPA_ABORT (1UL << 20) 22*54fd6939SJiyong Park 23*54fd6939SJiyong Park /* SMMU_S_IDR1 register fields */ 24*54fd6939SJiyong Park #define SMMU_S_IDR1_SECURE_IMPL (1UL << 31) 25*54fd6939SJiyong Park 26*54fd6939SJiyong Park /* SMMU_S_INIT register fields */ 27*54fd6939SJiyong Park #define SMMU_S_INIT_INV_ALL (1UL << 0) 28*54fd6939SJiyong Park 29*54fd6939SJiyong Park /* SMMU_S_GBPA register fields */ 30*54fd6939SJiyong Park #define SMMU_S_GBPA_UPDATE (1UL << 31) 31*54fd6939SJiyong Park #define SMMU_S_GBPA_ABORT (1UL << 20) 32*54fd6939SJiyong Park 33*54fd6939SJiyong Park int smmuv3_init(uintptr_t smmu_base); 34*54fd6939SJiyong Park int smmuv3_security_init(uintptr_t smmu_base); 35*54fd6939SJiyong Park 36*54fd6939SJiyong Park #endif /* SMMU_V3_H */ 37