1*54fd6939SJiyong Park /* 2*54fd6939SJiyong Park * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3*54fd6939SJiyong Park * 4*54fd6939SJiyong Park * SPDX-License-Identifier: BSD-3-Clause 5*54fd6939SJiyong Park */ 6*54fd6939SJiyong Park 7*54fd6939SJiyong Park #ifndef GIC_COMMON_H 8*54fd6939SJiyong Park #define GIC_COMMON_H 9*54fd6939SJiyong Park 10*54fd6939SJiyong Park #include <lib/utils_def.h> 11*54fd6939SJiyong Park 12*54fd6939SJiyong Park /******************************************************************************* 13*54fd6939SJiyong Park * GIC Distributor interface general definitions 14*54fd6939SJiyong Park ******************************************************************************/ 15*54fd6939SJiyong Park /* Constants to categorise interrupts */ 16*54fd6939SJiyong Park #define MIN_SGI_ID U(0) 17*54fd6939SJiyong Park #define MIN_SEC_SGI_ID U(8) 18*54fd6939SJiyong Park #define MIN_PPI_ID U(16) 19*54fd6939SJiyong Park #define MIN_SPI_ID U(32) 20*54fd6939SJiyong Park #define MAX_SPI_ID U(1019) 21*54fd6939SJiyong Park 22*54fd6939SJiyong Park #define TOTAL_SPI_INTR_NUM (MAX_SPI_ID - MIN_SPI_ID + U(1)) 23*54fd6939SJiyong Park #define TOTAL_PCPU_INTR_NUM (MIN_SPI_ID - MIN_SGI_ID) 24*54fd6939SJiyong Park 25*54fd6939SJiyong Park /* Mask for the priority field common to all GIC interfaces */ 26*54fd6939SJiyong Park #define GIC_PRI_MASK U(0xff) 27*54fd6939SJiyong Park 28*54fd6939SJiyong Park /* Mask for the configuration field common to all GIC interfaces */ 29*54fd6939SJiyong Park #define GIC_CFG_MASK U(0x3) 30*54fd6939SJiyong Park 31*54fd6939SJiyong Park /* Constant to indicate a spurious interrupt in all GIC versions */ 32*54fd6939SJiyong Park #define GIC_SPURIOUS_INTERRUPT U(1023) 33*54fd6939SJiyong Park 34*54fd6939SJiyong Park /* Interrupt configurations: 2-bit fields with LSB reserved */ 35*54fd6939SJiyong Park #define GIC_INTR_CFG_LEVEL (0 << 1) 36*54fd6939SJiyong Park #define GIC_INTR_CFG_EDGE (1 << 1) 37*54fd6939SJiyong Park 38*54fd6939SJiyong Park /* Highest possible interrupt priorities */ 39*54fd6939SJiyong Park #define GIC_HIGHEST_SEC_PRIORITY U(0x00) 40*54fd6939SJiyong Park #define GIC_HIGHEST_NS_PRIORITY U(0x80) 41*54fd6939SJiyong Park 42*54fd6939SJiyong Park /******************************************************************************* 43*54fd6939SJiyong Park * Common GIC Distributor interface register offsets 44*54fd6939SJiyong Park ******************************************************************************/ 45*54fd6939SJiyong Park #define GICD_CTLR U(0x0) 46*54fd6939SJiyong Park #define GICD_TYPER U(0x4) 47*54fd6939SJiyong Park #define GICD_IIDR U(0x8) 48*54fd6939SJiyong Park #define GICD_IGROUPR U(0x80) 49*54fd6939SJiyong Park #define GICD_ISENABLER U(0x100) 50*54fd6939SJiyong Park #define GICD_ICENABLER U(0x180) 51*54fd6939SJiyong Park #define GICD_ISPENDR U(0x200) 52*54fd6939SJiyong Park #define GICD_ICPENDR U(0x280) 53*54fd6939SJiyong Park #define GICD_ISACTIVER U(0x300) 54*54fd6939SJiyong Park #define GICD_ICACTIVER U(0x380) 55*54fd6939SJiyong Park #define GICD_IPRIORITYR U(0x400) 56*54fd6939SJiyong Park #define GICD_ICFGR U(0xc00) 57*54fd6939SJiyong Park #define GICD_NSACR U(0xe00) 58*54fd6939SJiyong Park 59*54fd6939SJiyong Park /* GICD_CTLR bit definitions */ 60*54fd6939SJiyong Park #define CTLR_ENABLE_G0_SHIFT 0 61*54fd6939SJiyong Park #define CTLR_ENABLE_G0_MASK U(0x1) 62*54fd6939SJiyong Park #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT) 63*54fd6939SJiyong Park 64*54fd6939SJiyong Park /******************************************************************************* 65*54fd6939SJiyong Park * Common GIC Distributor interface register constants 66*54fd6939SJiyong Park ******************************************************************************/ 67*54fd6939SJiyong Park #define PIDR2_ARCH_REV_SHIFT 4 68*54fd6939SJiyong Park #define PIDR2_ARCH_REV_MASK U(0xf) 69*54fd6939SJiyong Park 70*54fd6939SJiyong Park /* GIC revision as reported by PIDR2.ArchRev register field */ 71*54fd6939SJiyong Park #define ARCH_REV_GICV1 U(0x1) 72*54fd6939SJiyong Park #define ARCH_REV_GICV2 U(0x2) 73*54fd6939SJiyong Park #define ARCH_REV_GICV3 U(0x3) 74*54fd6939SJiyong Park #define ARCH_REV_GICV4 U(0x4) 75*54fd6939SJiyong Park 76*54fd6939SJiyong Park #define IGROUPR_SHIFT 5 77*54fd6939SJiyong Park #define ISENABLER_SHIFT 5 78*54fd6939SJiyong Park #define ICENABLER_SHIFT ISENABLER_SHIFT 79*54fd6939SJiyong Park #define ISPENDR_SHIFT 5 80*54fd6939SJiyong Park #define ICPENDR_SHIFT ISPENDR_SHIFT 81*54fd6939SJiyong Park #define ISACTIVER_SHIFT 5 82*54fd6939SJiyong Park #define ICACTIVER_SHIFT ISACTIVER_SHIFT 83*54fd6939SJiyong Park #define IPRIORITYR_SHIFT 2 84*54fd6939SJiyong Park #define ITARGETSR_SHIFT 2 85*54fd6939SJiyong Park #define ICFGR_SHIFT 4 86*54fd6939SJiyong Park #define NSACR_SHIFT 4 87*54fd6939SJiyong Park 88*54fd6939SJiyong Park /* GICD_TYPER shifts and masks */ 89*54fd6939SJiyong Park #define TYPER_IT_LINES_NO_SHIFT U(0) 90*54fd6939SJiyong Park #define TYPER_IT_LINES_NO_MASK U(0x1f) 91*54fd6939SJiyong Park 92*54fd6939SJiyong Park /* Value used to initialize Normal world interrupt priorities four at a time */ 93*54fd6939SJiyong Park #define GICD_IPRIORITYR_DEF_VAL \ 94*54fd6939SJiyong Park (GIC_HIGHEST_NS_PRIORITY | \ 95*54fd6939SJiyong Park (GIC_HIGHEST_NS_PRIORITY << 8) | \ 96*54fd6939SJiyong Park (GIC_HIGHEST_NS_PRIORITY << 16) | \ 97*54fd6939SJiyong Park (GIC_HIGHEST_NS_PRIORITY << 24)) 98*54fd6939SJiyong Park 99*54fd6939SJiyong Park #endif /* GIC_COMMON_H */ 100